mirror of https://github.com/YosysHQ/yosys.git
41 lines
1.0 KiB
Systemverilog
41 lines
1.0 KiB
Systemverilog
module pass_through(
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input [63:0] inp,
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output [63:0] out
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);
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assign out = inp;
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endmodule
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module top;
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logic [63:0]
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o01, o02, o03, o04,
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o05, o06, o07, o08,
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o09, o10, o11, o12,
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o13, o14, o15, o16;
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assign o01 = '0;
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assign o02 = '1;
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assign o03 = 'x;
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assign o04 = 'z;
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assign o05 = 3'('0);
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assign o06 = 3'('1);
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assign o07 = 3'('x);
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assign o08 = 3'('z);
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pass_through pt09('0, o09);
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pass_through pt10('1, o10);
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pass_through pt11('x, o11);
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pass_through pt12('z, o12);
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always @* begin
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assert (o01 === {64 {1'b0}});
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assert (o02 === {64 {1'b1}});
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assert (o03 === {64 {1'bx}});
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assert (o04 === {64 {1'bz}});
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assert (o05 === {61'b0, 3'b000});
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assert (o06 === {61'b0, 3'b111});
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assert (o07 === {61'b0, 3'bxxx});
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assert (o08 === {61'b0, 3'bzzz});
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assert (o09 === {64 {1'b0}});
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assert (o10 === {64 {1'b1}});
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assert (o11 === {64 {1'bx}});
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assert (o12 === {64 {1'bz}});
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end
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endmodule
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