mirror of https://github.com/YosysHQ/yosys.git
56 lines
937 B
Plaintext
56 lines
937 B
Plaintext
logger -expect-no-warnings
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read_verilog -formal <<EOT
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module top(input clk);
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reg [-1:-1] x;
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reg good = 0;
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reg signed [31:0] zero = 0;
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always @(posedge clk) begin
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case ($left(x) + zero) 36'shfffffffff: good = 1; endcase
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assert (good);
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end
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endmodule
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EOT
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prep -top top
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async2sync
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sim -n 3 -clock clk
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design -reset
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read_verilog -formal <<EOT
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module top(input clk);
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reg [-1:-1] x;
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reg good = 0;
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always @(posedge clk) begin
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case ($left(x)) 36'sh0ffffffff: good = 1; (32'h0 + $left(good)): ; endcase
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assert (good);
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end
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endmodule
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EOT
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prep -top top
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async2sync
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sim -n 3 -clock clk
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design -reset
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read_verilog -formal <<EOT
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module top(input clk);
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reg [-1:-1] x;
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reg good = 1;
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always @(posedge clk) begin
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case (36'sh100000000 + $left(x)) -1: good = 0; endcase
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assert (good);
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end
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endmodule
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EOT
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prep -top top
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async2sync
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sim -n 3 -clock clk
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