mirror of https://github.com/YosysHQ/yosys.git
29 lines
591 B
Systemverilog
29 lines
591 B
Systemverilog
`default_nettype none
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module gate(x, y);
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output reg [15:0] x, y;
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if (1) begin : gen
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integer x, y;
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for (genvar x = 0; x < 2; x++)
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if (x == 0)
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initial gen.x = 10;
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assign y = x + 1;
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end
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initial x = gen.x;
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assign y = gen.y;
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endmodule
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module gold(x, y);
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output reg [15:0] x, y;
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if (1) begin : gen
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integer x, y;
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genvar z;
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for (z = 0; z < 2; z++)
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if (z == 0)
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initial x = 10;
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assign y = x + 1;
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end
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initial x = gen.x;
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assign y = gen.y;
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endmodule
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