mirror of https://github.com/YosysHQ/yosys.git
31 lines
659 B
Systemverilog
31 lines
659 B
Systemverilog
`default_nettype none
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module gate(out);
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wire [3:0] x;
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for (genvar x = 0; x < 2; x++) begin : blk
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localparam w = x;
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if (x == 0) begin : sub
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wire [w:0] x;
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end
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end
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assign x = 2;
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assign blk[0].sub.x = '1;
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output wire [9:0] out;
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assign out = {1'bx, x, blk[0].sub.x};
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endmodule
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module gold(out);
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wire [3:0] x;
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genvar z;
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for (z = 0; z < 2; z++) begin : blk
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localparam w = z;
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if (z == 0) begin : sub
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wire [w:0] x;
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end
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end
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assign x = 2;
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assign blk[0].sub.x = '1;
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output wire [9:0] out;
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assign out = {1'bx, x, blk[0].sub.x};
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endmodule
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