mirror of https://github.com/YosysHQ/yosys.git
15 lines
354 B
Plaintext
15 lines
354 B
Plaintext
read_verilog -sv genvar_loop_decl_1.sv
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select -assert-count 1 gate/genblk1[0].x
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select -assert-count 1 gate/genblk1[1].x
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select -assert-count 0 gate/genblk1[2].x
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select -assert-count 1 gold/genblk1[0].x
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select -assert-count 1 gold/genblk1[1].x
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select -assert-count 0 gold/genblk1[2].x
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proc
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equiv_make gold gate equiv
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equiv_simple
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equiv_status -assert
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