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module top;
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parameter YES = 1;
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generate
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if (YES) wire y;
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else wire n;
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if (!YES) wire n;
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else wire y;
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case (YES)
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1: wire y;
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0: wire n;
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endcase
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case (!YES)
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0: wire y;
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1: wire n;
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endcase
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if (YES) wire y;
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else wire n;
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if (!YES) wire n;
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else wire y;
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endgenerate
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endmodule
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