mirror of https://github.com/YosysHQ/yosys.git
43 lines
1.1 KiB
Systemverilog
43 lines
1.1 KiB
Systemverilog
module top;
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function automatic [30:0] func;
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input integer inp;
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func = { // self-determined context
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(
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inp == 0
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? -1 // causes whole ternary to be 32 bits
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: func(inp - 1) // 31 bits, unsigned
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) >> 2};
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endfunction
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function automatic signed [3:0] dunk;
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input integer inp;
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dunk = (
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inp == 0
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? 4'hF
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// shouldn't make the ternary signed
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: dunk(inp - 1)
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) == -1;
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endfunction
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localparam A = func(0);
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localparam B = func(1);
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localparam C = func(2);
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localparam D = func(3);
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localparam X = dunk(0);
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localparam Y = dunk(1);
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initial begin
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assert(A == 31'h3F_FFFFFF);
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assert(B == 31'h0F_FFFFFF);
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assert(C == 31'h03_FFFFFF);
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assert(D == 31'h00_FFFFFF);
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assert(X == 0);
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assert(Y == 0);
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end
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initial begin
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logic x;
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case (1'b1)
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dunk(0): x = 0;
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default: x = 1;
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endcase
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assert(x);
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end
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endmodule
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