mirror of https://github.com/YosysHQ/yosys.git
74 lines
1.8 KiB
Systemverilog
74 lines
1.8 KiB
Systemverilog
module top;
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integer x, y, z;
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task check;
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input integer a, b, c;
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assert (x == a);
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assert (y == b);
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assert (z == c);
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endtask
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always_comb begin
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x = 0; y = 0; z = 0;
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check(0, 0, 0);
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// post-increment/decrement statements
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x++;
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check(1, 0, 0);
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(* bar *) y (* foo *) ++;
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check(1, 1, 0);
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z--;
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check(1, 1, -1);
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(* bar *) z (* foo *) --;
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check(1, 1, -2);
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// pre-increment/decrement statements are equivalent
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++z;
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check(1, 1, -1);
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(* bar *) ++ (* foo *) z;
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check(1, 1, 0);
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--x;
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check(0, 1, 0);
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(* bar *) -- (* foo *) y;
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check(0, 0, 0);
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// procedural pre-increment/decrement expressions
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z = ++x;
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check(1, 0, 1);
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z = ++ (* foo *) x;
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check(2, 0, 2);
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y = --x;
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check(1, 1, 2);
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y = -- (* foo *) x;
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// procedural post-increment/decrement expressions
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// TODO: support attributes on post-increment/decrement
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check(0, 0, 2);
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y = x++;
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check(1, 0, 2);
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y = x--;
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check(0, 1, 2);
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// procedural assignment expressions
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x = (y = (z = 99) + 1) + 1;
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check(101, 100, 99);
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x = (y *= 2);
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check(200, 200, 99);
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x = (z >>= 2) * 4;
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check(96, 200, 24);
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y = (z >>= 1'sb1) * 2; // shift is implicitly cast to unsigned
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check(96, 24, 12);
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// check width of post-increment expressions
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z = (y = 0);
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begin
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byte w;
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w = 0;
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x = {1'b1, ++w};
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check(257, 0, 0);
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assert (w == 1);
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x = {2'b10, w++};
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check(513, 0, 0);
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assert (w == 2);
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end
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end
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endmodule
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