mirror of https://github.com/YosysHQ/yosys.git
78 lines
1.5 KiB
Plaintext
78 lines
1.5 KiB
Plaintext
verific -sv <<EOF
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module rom(input clk, input [2:0] addr, (* ram_style = "block" *) output reg [7:0] data);
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always @(posedge clk) begin
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case (addr)
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3'b000: data <= 8'h12;
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3'b001: data <= 8'hAB;
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3'b010: data <= 8'h42;
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3'b011: data <= 8'h23;
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3'b100: data <= 8'h66;
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3'b101: data <= 8'hC0;
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3'b110: data <= 8'h3F;
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3'b111: data <= 8'h95;
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endcase
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end
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endmodule
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EOF
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hierarchy -top rom
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proc
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opt
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opt -full
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memory -nomap
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dump
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memory_libmap -lib ../memlib/memlib_block_sdp.txt
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memory_map
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stat
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select -assert-count 1 t:RAM_BLOCK_SDP
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design -reset
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verific -vhdl <<EOF
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library IEEE;
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use IEEE.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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entity rom_example is
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port (
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clk : in std_logic;
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addr : in std_logic_vector(2 downto 0);
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data : out std_logic_vector (7 downto 0)
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);
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end entity rom_example;
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architecture rtl of rom_example is
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attribute rom_style : string;
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attribute rom_style of data : signal is "block";
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begin
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p_rom : process(clk)
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begin
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if rising_edge(clk) then
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case addr is
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when "000" => data <= X"12";
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when "001" => data <= X"AB";
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when "010" => data <= X"42";
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when "011" => data <= X"23";
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when "100" => data <= X"66";
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when "101" => data <= X"C0";
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when "110" => data <= X"3F";
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when others => data <= X"95";
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end case;
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end if;
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end process p_rom;
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end architecture rtl;
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EOF
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hierarchy -top rom_example
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proc
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opt
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opt -full
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memory -nomap
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dump
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memory_libmap -lib ../memlib/memlib_block_sdp.txt
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memory_map
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stat
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select -assert-count 1 t:RAM_BLOCK_SDP |