mirror of https://github.com/YosysHQ/yosys.git
44 lines
813 B
Systemverilog
44 lines
813 B
Systemverilog
module dut();
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typedef struct packed {
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logic a;
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logic b;
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} sub_sub_struct_t;
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typedef struct packed {
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sub_sub_struct_t c;
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} sub_struct_t;
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typedef struct packed {
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sub_struct_t d;
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sub_struct_t e;
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} struct_t;
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parameter struct_t P = 4'b1100;
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localparam sub_struct_t f = P.d;
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localparam sub_struct_t g = P.e;
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localparam sub_sub_struct_t h = f.c;
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localparam logic i = P.d.c.a;
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localparam logic j = P.d.c.b;
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localparam x = P.e;
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localparam y = x.c;
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localparam z = y.a;
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localparam q = P.d;
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localparam n = q.c.a;
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always_comb begin
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assert(P == 4'b1100);
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assert(f == 2'b11);
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assert(g == 2'b00);
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assert(h == 2'b11);
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assert(i == 1'b1);
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assert(j == 1'b1);
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assert(x == 2'b00);
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assert(y == 2'b00);
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assert(x.c == 2'b00);
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assert(y.b == 1'b0);
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assert(n == 1'b1);
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assert(z == 1'b0);
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end
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endmodule
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