mirror of https://github.com/YosysHQ/yosys.git
52 lines
920 B
Plaintext
52 lines
920 B
Plaintext
read_verilog -sv << EOF
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package p;
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typedef struct packed {
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logic a;
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logic b;
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} struct_t;
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typedef struct packed {
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struct_t g;
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logic [2:0] h;
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} nested_struct_t;
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typedef union packed {
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logic [4:0] x;
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} nested_union_t;
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parameter struct_t c = {1'b1, 1'b0};
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parameter nested_struct_t x = {{1'b1, 1'b0}, 1'b1, 1'b1, 1'b1};
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endpackage
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module dut ();
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parameter p::struct_t d = p::c;
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parameter p::nested_struct_t i = p::x;
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parameter p::nested_union_t u = {5'b11001};
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localparam e = d.a;
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localparam f = d.b;
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localparam j = i.g.a;
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localparam k = i.g.b;
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localparam l = i.h;
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localparam m = i.g;
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localparam o = u.x;
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always_comb begin
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assert(d == 2'b10);
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assert(e == 1'b1);
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assert(f == 1'b0);
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assert(j == 1'b1);
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assert(k == 1'b0);
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assert(l == 3'b111);
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assert(m == 2'b10);
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assert(u == 5'b11001);
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end
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endmodule
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EOF
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hierarchy; proc; opt
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async2sync
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sat -verify -seq 1 -tempinduct -prove-asserts -show-all
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