mirror of https://github.com/YosysHQ/yosys.git
551 lines
13 KiB
Plaintext
551 lines
13 KiB
Plaintext
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read_verilog -formal <<EOT
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module gate (input [2:0] A, B, C, D, X, output reg [2:0] Y);
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always @*
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(* parallel_case *)
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casez (X)
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3'b??1: Y = A;
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3'b?1?: Y = B;
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3'b1??: Y = C;
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3'b000: Y = D;
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endcase
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endmodule
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EOT
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## Example usage for "pmuxtree" and "muxcover"
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proc
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pmuxtree
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techmap
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muxcover -mux4
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splitnets -ports
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clean
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# show
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## Equivalence checking
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read_verilog -formal <<EOT
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module gold (input [2:0] A, B, C, D, X, output reg [2:0] Y);
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always @*
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casez (X)
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3'b001: Y = A;
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3'b010: Y = B;
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3'b100: Y = C;
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3'b000: Y = D;
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default: Y = 'bx;
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endcase
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endmodule
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EOT
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proc
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splitnets -ports
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techmap -map +/simcells.v t:$_MUX4_
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equiv_make gold gate equiv
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hierarchy -top equiv
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equiv_simple -undef
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equiv_status -assert
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## Partial matching MUX4
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design -reset
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read_verilog -formal <<EOT
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module mux_if_bal_3_1 #(parameter N=3, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
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always @* begin
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o <= {{W{{1'bx}}}};
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if (s[0] == 1'b0)
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if (s[1] == 1'b0)
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o <= i[0*W+:W];
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else
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o <= i[1*W+:W];
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else
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if (s[1] == 1'b0)
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o <= i[2*W+:W];
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end
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endmodule
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EOT
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prep
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design -save gold
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techmap
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muxcover -mux4=150
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select -assert-count 0 t:$_MUX_
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select -assert-count 1 t:$_MUX4_
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select -assert-count 0 t:$_MUX8_
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select -assert-count 0 t:$_MUX16_
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techmap -map +/simcells.v t:$_MUX4_
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports miter
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## Partial matching MUX8
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design -reset
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read_verilog -formal <<EOT
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module mux_if_bal_5_1 #(parameter N=5, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
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always @* begin
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o <= {{W{{1'bx}}}};
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if (s[0] == 1'b0)
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if (s[1] == 1'b0)
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if (s[2] == 1'b0)
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o <= i[0*W+:W];
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else
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o <= i[1*W+:W];
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else
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if (s[2] == 1'b0)
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o <= i[2*W+:W];
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else
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o <= i[3*W+:W];
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else
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if (s[1] == 1'b0)
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if (s[2] == 1'b0)
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o <= i[4*W+:W];
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end
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endmodule
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EOT
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prep
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design -save gold
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techmap
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muxcover -mux4=150 -mux8=200
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clean
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opt_expr -mux_bool
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select -assert-count 0 t:$_MUX_
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select -assert-count 0 t:$_MUX4_
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select -assert-count 1 t:$_MUX8_
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select -assert-count 0 t:$_MUX16_
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techmap -map +/simcells.v t:$_MUX8_
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports miter
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## Partial matching MUX16
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design -reset
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read_verilog -formal <<EOT
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module mux_if_bal_9_1 #(parameter N=9, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
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always @* begin
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o <= {{W{{1'bx}}}};
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if (s[0] == 1'b0)
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if (s[1] == 1'b0)
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if (s[2] == 1'b0)
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if (s[3] == 1'b0)
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o <= i[0*W+:W];
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else
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o <= i[1*W+:W];
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else
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if (s[3] == 1'b0)
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o <= i[2*W+:W];
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else
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o <= i[3*W+:W];
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else
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if (s[2] == 1'b0)
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if (s[3] == 1'b0)
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o <= i[4*W+:W];
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else
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o <= i[5*W+:W];
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else
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if (s[3] == 1'b0)
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o <= i[6*W+:W];
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else
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o <= i[7*W+:W];
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else
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if (s[1] == 1'b0)
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if (s[2] == 1'b0)
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if (s[3] == 1'b0)
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o <= i[8*W+:W];
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end
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endmodule
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EOT
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prep
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design -save gold
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techmap
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muxcover -mux4=150 -mux8=200 -mux16=250
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clean
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opt_expr -mux_bool
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select -assert-count 0 t:$_MUX_
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select -assert-count 0 t:$_MUX4_
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select -assert-count 0 t:$_MUX8_
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select -assert-count 1 t:$_MUX16_
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techmap -map +/simcells.v t:$_MUX16_
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports miter
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## MUX2 in MUX4 :: https://github.com/YosysHQ/yosys/issues/1132
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design -reset
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read_verilog -formal <<EOT
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module mux2in4(input [1:0] i, input s, output o);
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assign o = s ? i[1] : i[0];
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endmodule
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EOT
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prep
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design -save gold
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techmap
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muxcover -mux4=99 -nodecode
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clean
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opt_expr -mux_bool
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select -assert-count 0 t:$_MUX_
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select -assert-count 1 t:$_MUX4_
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select -assert-count 0 t:$_MUX8_
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select -assert-count 0 t:$_MUX16_
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techmap -map +/simcells.v t:$_MUX4_
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports miter
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## MUX2 in MUX8 :: https://github.com/YosysHQ/yosys/issues/1132
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design -reset
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read_verilog -formal <<EOT
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module mux2in8(input [1:0] i, input s, output o);
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assign o = s ? i[1] : i[0];
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endmodule
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EOT
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prep
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design -save gold
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techmap
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muxcover -mux8=99 -nodecode
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clean
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opt_expr -mux_bool
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select -assert-count 0 t:$_MUX_
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select -assert-count 0 t:$_MUX4_
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select -assert-count 1 t:$_MUX8_
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select -assert-count 0 t:$_MUX16_
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techmap -map +/simcells.v t:$_MUX8_
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports miter
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## MUX4 in MUX8 :: https://github.com/YosysHQ/yosys/issues/1132
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design -reset
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read_verilog -formal <<EOT
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module mux4in8(input [3:0] i, input [1:0] s, output o);
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assign o = s[1] ? (s[0] ? i[3] : i[2]) : (s[0] ? i[1] : i[0]);
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endmodule
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EOT
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prep
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design -save gold
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techmap
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muxcover -mux8=299 -nodecode
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clean
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opt_expr -mux_bool
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select -assert-count 0 t:$_MUX_
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select -assert-count 0 t:$_MUX4_
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select -assert-count 1 t:$_MUX8_
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select -assert-count 0 t:$_MUX16_
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techmap -map +/simcells.v t:$_MUX8_
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports miter
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## MUX2 in MUX16 :: https://github.com/YosysHQ/yosys/issues/1132
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design -reset
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read_verilog -formal <<EOT
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module mux2in16(input [1:0] i, input s, output o);
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assign o = s ? i[1] : i[0];
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endmodule
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EOT
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prep
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design -save gold
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techmap
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muxcover -mux16=99 -nodecode
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clean
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opt_expr -mux_bool
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select -assert-count 0 t:$_MUX_
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select -assert-count 0 t:$_MUX4_
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select -assert-count 0 t:$_MUX8_
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select -assert-count 1 t:$_MUX16_
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techmap -map +/simcells.v t:$_MUX16_
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports miter
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## MUX4 in MUX16 :: https://github.com/YosysHQ/yosys/issues/1132
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design -reset
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read_verilog -formal <<EOT
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module mux4in16(input [3:0] i, input [1:0] s, output o);
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assign o = s[1] ? (s[0] ? i[3] : i[2]) : (s[0] ? i[1] : i[0]);
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endmodule
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EOT
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prep
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design -save gold
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techmap
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muxcover -mux16=299 -nodecode
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clean
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opt_expr -mux_bool
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select -assert-count 0 t:$_MUX_
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select -assert-count 0 t:$_MUX4_
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select -assert-count 0 t:$_MUX8_
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select -assert-count 1 t:$_MUX16_
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techmap -map +/simcells.v t:$_MUX16_
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports miter
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## MUX8 in MUX16 :: https://github.com/YosysHQ/yosys/issues/1132
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design -reset
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read_verilog -formal <<EOT
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module mux4in16(input [7:0] i, input [2:0] s, output o);
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assign o = s[2] ? s[1] ? (s[0] ? i[3] : i[2]) : (s[0] ? i[1] : i[0])
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: s[1] ? (s[0] ? i[7] : i[6]) : (s[0] ? i[5] : i[4]);
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endmodule
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EOT
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prep
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design -save gold
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techmap
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muxcover -mux16=699 -nodecode
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clean
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opt_expr -mux_bool
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select -assert-count 0 t:$_MUX_
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select -assert-count 0 t:$_MUX4_
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select -assert-count 0 t:$_MUX8_
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select -assert-count 1 t:$_MUX16_
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techmap -map +/simcells.v t:$_MUX16_
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports miter
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## mux_if_bal_5_1 :: https://github.com/YosysHQ/yosys/issues/1132
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design -reset
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read_verilog -formal <<EOT
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module mux_if_bal_5_1 #(parameter N=5, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
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always @* begin
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o <= {{W{{1'bx}}}};
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if (s[0] == 1'b0)
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if (s[1] == 1'b0)
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if (s[2] == 1'b0)
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o <= i[0*W+:W];
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else
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o <= i[1*W+:W];
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else
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if (s[2] == 1'b0)
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o <= i[2*W+:W];
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else
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o <= i[3*W+:W];
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else
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if (s[1] == 1'b0)
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if (s[2] == 1'b0)
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o <= i[4*W+:W];
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end
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endmodule
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EOT
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prep
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design -save gold
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wreduce
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opt -full
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techmap
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muxcover -mux8=350
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clean
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opt_expr -mux_bool
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select -assert-count 0 t:$_MUX_
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select -assert-count 0 t:$_MUX4_
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select -assert-count 1 t:$_MUX8_
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select -assert-count 0 t:$_MUX16_
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techmap -map +/simcells.v t:$_MUX8_
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs -ignore_gold_x gold gate miter
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sat -verify -prove-asserts -show-ports miter
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## mux_if_bal_5_1 (nodecode) :: https://github.com/YosysHQ/yosys/issues/1132
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design -load gold
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wreduce
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opt -full
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techmap
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muxcover -mux8=350 -nodecode
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clean
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opt_expr -mux_bool
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select -assert-count 0 t:$_MUX_
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select -assert-count 0 t:$_MUX4_
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select -assert-count 1 t:$_MUX8_
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select -assert-count 0 t:$_MUX16_
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techmap -map +/simcells.v t:$_MUX8_
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs -ignore_gold_x gold gate miter
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sat -verify -prove-asserts -show-ports miter
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## mux_if_bal_9_1 :: https://github.com/YosysHQ/yosys/issues/1132
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design -reset
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read_verilog -formal <<EOT
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module mux_if_bal_9_1 #(parameter N=9, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
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always @* begin
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o <= {{W{{1'bx}}}};
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if (s[3] == 1'b0)
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if (s[2] == 1'b0)
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if (s[1] == 1'b0)
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if (s[0] == 1'b0)
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o <= i[0*W+:W];
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else
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o <= i[1*W+:W];
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else
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if (s[0] == 1'b0)
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o <= i[2*W+:W];
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else
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o <= i[3*W+:W];
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else
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if (s[1] == 1'b0)
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if (s[0] == 1'b0)
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o <= i[4*W+:W];
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else
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o <= i[5*W+:W];
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else
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if (s[0] == 1'b0)
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o <= i[6*W+:W];
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else
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o <= i[7*W+:W];
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else
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if (s[2] == 1'b0)
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if (s[1] == 1'b0)
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if (s[0] == 1'b0)
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o <= i[8*W+:W];
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end
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endmodule
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EOT
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prep
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design -save gold
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wreduce
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opt -full
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techmap
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muxcover -mux16=750
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clean
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opt_expr -mux_bool
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select -assert-count 0 t:$_MUX_
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select -assert-count 0 t:$_MUX4_
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select -assert-count 0 t:$_MUX8_
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select -assert-count 1 t:$_MUX16_
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techmap -map +/simcells.v t:$_MUX16_
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs -ignore_gold_x gold gate miter
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sat -verify -prove-asserts -show-ports miter
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## mux_if_bal_9_1 (nodecode) :: https://github.com/YosysHQ/yosys/issues/1132
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design -load gold
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wreduce
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opt -full
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techmap
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muxcover -mux16=750 -nodecode
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clean
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opt_expr -mux_bool
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select -assert-count 0 t:$_MUX_
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select -assert-count 0 t:$_MUX4_
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select -assert-count 0 t:$_MUX8_
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select -assert-count 1 t:$_MUX16_
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techmap -map +/simcells.v t:$_MUX16_
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs -ignore_gold_x gold gate miter
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sat -verify -prove-asserts -show-ports miter
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## implement a mux6 as a mux8 :: https://github.com/YosysHQ/yosys/issues/3591
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design -reset
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read_verilog << EOF
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module test (A, S, Y);
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parameter INPUTS = 6;
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input [INPUTS-1:0] A;
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input [$clog2(INPUTS)-1:0] S;
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wire [15:0] AA = {{(16-INPUTS){1'b0}}, A};
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wire [3:0] SS = {{(4-$clog2(INPUTS)){1'b0}}, S};
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output Y = SS[3] ? (SS[2] ? SS[1] ? (SS[0] ? AA[15] : AA[14])
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: (SS[0] ? AA[13] : AA[12])
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: SS[1] ? (SS[0] ? AA[11] : AA[10])
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: (SS[0] ? AA[9] : AA[8]))
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: (SS[2] ? SS[1] ? (SS[0] ? AA[7] : AA[6])
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: (SS[0] ? AA[5] : AA[4])
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: SS[1] ? (SS[0] ? AA[3] : AA[2])
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: (SS[0] ? AA[1] : AA[0]));
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endmodule
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EOF
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prep
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design -save gold
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simplemap t:\$mux
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muxcover
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opt_clean -purge
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select -assert-count 1 t:$_MUX8_
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select -assert-none t:$_MUX8_ %% t:* %D
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techmap -map +/simcells.v t:$_MUX8_
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs -ignore_gold_x gold gate miter
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sat -verify -prove-asserts -show-ports miter
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