mirror of https://github.com/YosysHQ/yosys.git
21 lines
512 B
Plaintext
21 lines
512 B
Plaintext
read_verilog -icells <<EOF
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module top(input [2:0] a, input [2:0] b, output [2:0] y);
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sub sub_i (.a(a[0]), .b(b[0]), .y(y[0]));
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unknown_sub sub_ii (.a(a[1]), .b(b[1]), .y(y[1]));
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$__dunder_sub sub_iii (.a(a[2]), .b(b[2]), .y(y[2]));
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endmodule
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module sub(input a, input b, output y);
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assign y = a ^ b;
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endmodule
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EOF
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hierarchy -generate unknown_sub i:a i:b o:y
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hierarchy -generate $__dunder_sub i:a i:b o:y
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hierarchy -generate $xor i:A i:B o:Y # this one is ignored
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hierarchy -top top -check
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check -assert
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