mirror of https://github.com/YosysHQ/yosys.git
50 lines
1.3 KiB
Verilog
50 lines
1.3 KiB
Verilog
(* techmap_celltype = "$reduce_or" *)
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module my_opt_reduce_or(...);
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parameter A_SIGNED = 0;
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parameter A_WIDTH = 2;
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parameter Y_WIDTH = 1;
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input [A_WIDTH-1:0] A;
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output reg [Y_WIDTH-1:0] Y;
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parameter _TECHMAP_CONSTMSK_A_ = 0;
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parameter _TECHMAP_CONSTVAL_A_ = 0;
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wire _TECHMAP_FAIL_ = count_nonconst_bits() == A_WIDTH;
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wire [1024:0] _TECHMAP_DO_ = "proc;;";
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function integer count_nonconst_bits;
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integer i;
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begin
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count_nonconst_bits = 0;
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for (i = 0; i < A_WIDTH; i=i+1)
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if (!_TECHMAP_CONSTMSK_A_[i])
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count_nonconst_bits = count_nonconst_bits+1;
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end
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endfunction
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function has_const_one;
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integer i;
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begin
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has_const_one = 0;
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for (i = 0; i < A_WIDTH; i=i+1)
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if (_TECHMAP_CONSTMSK_A_[i] && _TECHMAP_CONSTVAL_A_[i] === 1'b1)
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has_const_one = 1;
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end
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endfunction
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integer i;
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reg [count_nonconst_bits()-1:0] tmp;
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always @* begin
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if (has_const_one()) begin
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Y = 1;
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end else begin
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for (i = 0; i < A_WIDTH; i=i+1)
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if (!_TECHMAP_CONSTMSK_A_[i])
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tmp = {A[i], tmp[count_nonconst_bits()-1:1]};
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Y = |tmp;
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end
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end
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endmodule
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