mirror of https://github.com/YosysHQ/yosys.git
16 lines
298 B
Plaintext
16 lines
298 B
Plaintext
read_verilog constmsk_test.v
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copy test gold
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rename test gate
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cd gate
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techmap -map constmsk_testmap.v;;
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cd ..
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select -assert-count 2 gold/r:A_WIDTH=3
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select -assert-count 1 gate/r:A_WIDTH=2
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select -assert-count 1 gate/c:*
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miter -equiv -flatten gold gate miter
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sat -verify -prove trigger 0 miter
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