mirror of https://github.com/YosysHQ/yosys.git
42 lines
984 B
Plaintext
42 lines
984 B
Plaintext
read_verilog << EOT
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module ff4(...);
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parameter [0:0] CLK_INV = 1'b0;
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parameter [3:0] DATA_INV = 4'b0000;
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(* invertible_pin = "CLK_INV" *)
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input clk;
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(* invertible_pin = "DATA_INV" *)
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input [3:0] d;
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output [3:0] q;
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endmodule
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module inv(...);
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output o;
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input i;
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endmodule
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module top(...);
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input d0, d1, d2, d3;
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input clk;
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output q;
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ff4 #(.DATA_INV(4'h5)) ff_inst (.clk(clk), .d({d3, d2, d1, d0}), .q(q));
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endmodule
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EOT
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extractinv -inv inv o:i
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clean
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select -assert-count 2 top/t:inv
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select -assert-count 2 top/t:inv top/t:ff4 %ci:+[d] %ci:+[o] %i
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select -assert-count 1 top/t:inv top/w:d0 %co:+[i] %i
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select -assert-count 0 top/t:inv top/w:d1 %co:+[i] %i
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select -assert-count 1 top/t:inv top/w:d2 %co:+[i] %i
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select -assert-count 0 top/t:inv top/w:d3 %co:+[i] %i
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select -assert-count 0 top/t:ff4 top/w:d0 %co:+[d] %i
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select -assert-count 1 top/t:ff4 top/w:d1 %co:+[d] %i
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select -assert-count 0 top/t:ff4 top/w:d2 %co:+[d] %i
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select -assert-count 1 top/t:ff4 top/w:d3 %co:+[d] %i
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