mirror of https://github.com/YosysHQ/yosys.git
192 lines
7.9 KiB
Plaintext
192 lines
7.9 KiB
Plaintext
# Base test: make sure inverters are applied correctly.
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read_verilog -icells <<EOT
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module top(input C, E, R, S, D, L, AD, output [71:0] Q);
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$_DFF_P_ ff0 (.C(C), .D(D), .Q(Q[0]));
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$_DFF_N_ ff1 (.C(C), .D(D), .Q(Q[1]));
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$_DFFE_PP_ ff2 (.C(C), .E(E), .D(D), .Q(Q[2]));
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$_DFFE_PN_ ff3 (.C(C), .E(E), .D(D), .Q(Q[3]));
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$_DFFE_NP_ ff4 (.C(C), .E(E), .D(D), .Q(Q[4]));
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$_DFF_PP0_ ff5 (.C(C), .R(R), .D(D), .Q(Q[5]));
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$_DFF_PN0_ ff6 (.C(C), .R(R), .D(D), .Q(Q[6]));
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$_DFF_NP0_ ff7 (.C(C), .R(R), .D(D), .Q(Q[7]));
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$_DFF_PP1_ ff8 (.C(C), .R(R), .D(D), .Q(Q[8]));
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$_DFF_PN1_ ff9 (.C(C), .R(R), .D(D), .Q(Q[9]));
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$_DFF_NP1_ ff10 (.C(C), .R(R), .D(D), .Q(Q[10]));
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$_DFFE_PP0P_ ff11 (.C(C), .R(R), .E(E), .D(D), .Q(Q[11]));
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$_DFFE_PP0N_ ff12 (.C(C), .R(R), .E(E), .D(D), .Q(Q[12]));
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$_DFFE_PN0P_ ff13 (.C(C), .R(R), .E(E), .D(D), .Q(Q[13]));
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$_DFFE_NP0P_ ff14 (.C(C), .R(R), .E(E), .D(D), .Q(Q[14]));
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$_DFFE_PP1P_ ff15 (.C(C), .R(R), .E(E), .D(D), .Q(Q[15]));
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$_DFFE_PP1N_ ff16 (.C(C), .R(R), .E(E), .D(D), .Q(Q[16]));
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$_DFFE_PN1P_ ff17 (.C(C), .R(R), .E(E), .D(D), .Q(Q[17]));
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$_DFFE_NP1P_ ff18 (.C(C), .R(R), .E(E), .D(D), .Q(Q[18]));
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$_DFFSR_PPP_ ff19 (.C(C), .R(R), .S(S), .D(D), .Q(Q[19]));
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$_DFFSR_PPN_ ff20 (.C(C), .R(R), .S(S), .D(D), .Q(Q[20]));
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$_DFFSR_PNP_ ff21 (.C(C), .R(R), .S(S), .D(D), .Q(Q[21]));
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$_DFFSR_NPP_ ff22 (.C(C), .R(R), .S(S), .D(D), .Q(Q[22]));
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$_DFFSRE_PPPP_ ff23 (.C(C), .R(R), .S(S), .E(E), .D(D), .Q(Q[23]));
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$_DFFSRE_PPPN_ ff24 (.C(C), .R(R), .S(S), .E(E), .D(D), .Q(Q[24]));
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$_DFFSRE_PPNP_ ff25 (.C(C), .R(R), .S(S), .E(E), .D(D), .Q(Q[25]));
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$_DFFSRE_PNPP_ ff26 (.C(C), .R(R), .S(S), .E(E), .D(D), .Q(Q[26]));
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$_DFFSRE_NPPP_ ff27 (.C(C), .R(R), .S(S), .E(E), .D(D), .Q(Q[27]));
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$_SDFF_PP0_ ff28 (.C(C), .R(R), .D(D), .Q(Q[28]));
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$_SDFF_PN0_ ff29 (.C(C), .R(R), .D(D), .Q(Q[29]));
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$_SDFF_NP0_ ff30 (.C(C), .R(R), .D(D), .Q(Q[30]));
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$_SDFF_PP1_ ff31 (.C(C), .R(R), .D(D), .Q(Q[31]));
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$_SDFF_PN1_ ff32 (.C(C), .R(R), .D(D), .Q(Q[32]));
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$_SDFF_NP1_ ff33 (.C(C), .R(R), .D(D), .Q(Q[33]));
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$_SDFFE_PP0P_ ff34 (.C(C), .R(R), .E(E), .D(D), .Q(Q[34]));
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$_SDFFE_PP0N_ ff35 (.C(C), .R(R), .E(E), .D(D), .Q(Q[35]));
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$_SDFFE_PN0P_ ff36 (.C(C), .R(R), .E(E), .D(D), .Q(Q[36]));
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$_SDFFE_NP0P_ ff37 (.C(C), .R(R), .E(E), .D(D), .Q(Q[37]));
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$_SDFFE_PP1P_ ff38 (.C(C), .R(R), .E(E), .D(D), .Q(Q[38]));
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$_SDFFE_PP1N_ ff39 (.C(C), .R(R), .E(E), .D(D), .Q(Q[39]));
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$_SDFFE_PN1P_ ff40 (.C(C), .R(R), .E(E), .D(D), .Q(Q[40]));
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$_SDFFE_NP1P_ ff41 (.C(C), .R(R), .E(E), .D(D), .Q(Q[41]));
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$_SDFFCE_PP0P_ ff42 (.C(C), .R(R), .E(E), .D(D), .Q(Q[42]));
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$_SDFFCE_PP0N_ ff43 (.C(C), .R(R), .E(E), .D(D), .Q(Q[43]));
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$_SDFFCE_PN0P_ ff44 (.C(C), .R(R), .E(E), .D(D), .Q(Q[44]));
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$_SDFFCE_NP0P_ ff45 (.C(C), .R(R), .E(E), .D(D), .Q(Q[45]));
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$_SDFFCE_PP1P_ ff46 (.C(C), .R(R), .E(E), .D(D), .Q(Q[46]));
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$_SDFFCE_PP1N_ ff47 (.C(C), .R(R), .E(E), .D(D), .Q(Q[47]));
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$_SDFFCE_PN1P_ ff48 (.C(C), .R(R), .E(E), .D(D), .Q(Q[48]));
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$_SDFFCE_NP1P_ ff49 (.C(C), .R(R), .E(E), .D(D), .Q(Q[49]));
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$_DLATCH_P_ ff50 (.E(E), .D(D), .Q(Q[50]));
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$_DLATCH_N_ ff51 (.E(E), .D(D), .Q(Q[51]));
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$_DLATCH_PP0_ ff52 (.E(E), .R(R), .D(D), .Q(Q[52]));
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$_DLATCH_PN0_ ff53 (.E(E), .R(R), .D(D), .Q(Q[53]));
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$_DLATCH_NP0_ ff54 (.E(E), .R(R), .D(D), .Q(Q[54]));
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$_DLATCH_PP1_ ff55 (.E(E), .R(R), .D(D), .Q(Q[55]));
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$_DLATCH_PN1_ ff56 (.E(E), .R(R), .D(D), .Q(Q[56]));
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$_DLATCH_NP1_ ff57 (.E(E), .R(R), .D(D), .Q(Q[57]));
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$_DLATCHSR_PPP_ ff58 (.E(E), .R(R), .S(S), .D(D), .Q(Q[58]));
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$_DLATCHSR_PPN_ ff59 (.E(E), .R(R), .S(S), .D(D), .Q(Q[59]));
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$_DLATCHSR_PNP_ ff60 (.E(E), .R(R), .S(S), .D(D), .Q(Q[60]));
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$_DLATCHSR_NPP_ ff61 (.E(E), .R(R), .S(S), .D(D), .Q(Q[61]));
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$_SR_PP_ ff62 (.R(R), .S(S), .Q(Q[62]));
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$_SR_PN_ ff63 (.R(R), .S(S), .Q(Q[63]));
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$_SR_NP_ ff64 (.R(R), .S(S), .Q(Q[64]));
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$_ALDFF_PP_ ff65 (.C(C), .L(L), .AD(AD), .D(D), .Q(Q[65]));
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$_ALDFF_PN_ ff66 (.C(C), .L(L), .AD(AD), .D(D), .Q(Q[66]));
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$_ALDFF_NP_ ff67 (.C(C), .L(L), .AD(AD), .D(D), .Q(Q[67]));
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$_ALDFFE_PPP_ ff68 (.C(C), .L(L), .AD(AD), .D(D), .E(E), .Q(Q[68]));
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$_ALDFFE_PPN_ ff69 (.C(C), .L(L), .AD(AD), .D(D), .E(E), .Q(Q[69]));
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$_ALDFFE_PNP_ ff70 (.C(C), .L(L), .AD(AD), .D(D), .E(E), .Q(Q[70]));
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$_ALDFFE_NPP_ ff71 (.C(C), .L(L), .AD(AD), .D(D), .E(E), .Q(Q[71]));
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endmodule
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EOT
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design -save orig
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equiv_opt -assert -multiclock dfflegalize -cell $_DFF_P_ x -cell $_DFFE_PP_ x -cell $_DFF_PP?_ x -cell $_DFFE_PP?P_ x -cell $_DFFSR_PPP_ x -cell $_DFFSRE_PPPP_ x -cell $_SDFF_PP?_ x -cell $_SDFFE_PP?P_ x -cell $_SDFFCE_PP?P_ x -cell $_DLATCH_P_ x -cell $_DLATCH_PP?_ x -cell $_DLATCHSR_PPP_ x -cell $_SR_PP_ x -cell $_ALDFF_PP_ x -cell $_ALDFFE_PPP_ x
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design -load postopt
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select -assert-count 51 t:$_NOT_
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select -assert-count 2 t:$_DFF_P_
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select -assert-count 3 t:$_DFFE_PP_
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select -assert-count 3 t:$_DFF_PP0_
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select -assert-count 3 t:$_DFF_PP1_
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select -assert-count 4 t:$_DFFE_PP0P_
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select -assert-count 4 t:$_DFFE_PP1P_
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select -assert-count 4 t:$_DFFSR_PPP_
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select -assert-count 5 t:$_DFFSRE_PPPP_
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select -assert-count 3 t:$_SDFF_PP0_
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select -assert-count 3 t:$_SDFF_PP1_
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select -assert-count 4 t:$_SDFFE_PP0P_
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select -assert-count 4 t:$_SDFFE_PP1P_
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select -assert-count 4 t:$_SDFFCE_PP0P_
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select -assert-count 4 t:$_SDFFCE_PP1P_
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select -assert-count 2 t:$_DLATCH_P_
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select -assert-count 3 t:$_DLATCH_PP0_
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select -assert-count 3 t:$_DLATCH_PP1_
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select -assert-count 4 t:$_DLATCHSR_PPP_
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select -assert-count 3 t:$_SR_PP_
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select -assert-count 3 t:$_ALDFF_PP_
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select -assert-count 4 t:$_ALDFFE_PPP_
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select -assert-none t:$_DFF_P_ t:$_DFFE_PP_ t:$_DFF_PP?_ t:$_DFFE_PP?P_ t:$_DFFSR_PPP_ t:$_DFFSRE_PPPP_ t:$_SDFF_PP?_ t:$_SDFFE_PP?P_ t:$_SDFFCE_PP?P_ t:$_DLATCH_P_ t:$_DLATCH_PP?_ t:$_DLATCHSR_PPP_ t:$_SR_PP_ t:$_ALDFF_PP_ t:$_ALDFFE_PPP_ t:$_NOT_ %% %n t:* %i
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# Now try it again, targetting the opposite cells.
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design -load orig
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equiv_opt -assert -multiclock dfflegalize -cell $_DFF_N_ x -cell $_DFFE_NN_ x -cell $_DFF_NN?_ x -cell $_DFFE_NN?N_ x -cell $_DFFSR_NNN_ x -cell $_DFFSRE_NNNN_ x -cell $_SDFF_NN?_ x -cell $_SDFFE_NN?N_ x -cell $_SDFFCE_NN?N_ x -cell $_DLATCH_N_ x -cell $_DLATCH_NN?_ x -cell $_DLATCHSR_NNN_ x -cell $_SR_NN_ x -cell $_ALDFF_NN_ x -cell $_ALDFFE_NNN_ x
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design -load postopt
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select -assert-count 135 t:$_NOT_
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select -assert-count 2 t:$_DFF_N_
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select -assert-count 3 t:$_DFFE_NN_
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select -assert-count 3 t:$_DFF_NN0_
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select -assert-count 3 t:$_DFF_NN1_
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select -assert-count 4 t:$_DFFE_NN0N_
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select -assert-count 4 t:$_DFFE_NN1N_
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select -assert-count 4 t:$_DFFSR_NNN_
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select -assert-count 5 t:$_DFFSRE_NNNN_
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select -assert-count 3 t:$_SDFF_NN0_
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select -assert-count 3 t:$_SDFF_NN1_
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select -assert-count 4 t:$_SDFFE_NN0N_
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select -assert-count 4 t:$_SDFFE_NN1N_
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select -assert-count 4 t:$_SDFFCE_NN0N_
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select -assert-count 4 t:$_SDFFCE_NN1N_
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select -assert-count 2 t:$_DLATCH_N_
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select -assert-count 3 t:$_DLATCH_NN0_
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select -assert-count 3 t:$_DLATCH_NN1_
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select -assert-count 4 t:$_DLATCHSR_NNN_
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select -assert-count 3 t:$_SR_NN_
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select -assert-count 3 t:$_ALDFF_NN_
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select -assert-count 4 t:$_ALDFFE_NNN_
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select -assert-none t:$_DFF_N_ t:$_DFFE_NN_ t:$_DFF_NN?_ t:$_DFFE_NN?N_ t:$_DFFSR_NNN_ t:$_DFFSRE_NNNN_ t:$_SDFF_NN?_ t:$_SDFFE_NN?N_ t:$_SDFFCE_NN?N_ t:$_DLATCH_N_ t:$_DLATCH_NN?_ t:$_DLATCHSR_NNN_ t:$_SR_NN_ t:$_ALDFF_NN_ t:$_ALDFFE_NNN_ t:$_NOT_ %% %n t:* %i
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# Second test: make sure set/reset/enable are inverted before clock.
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design -reset
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read_verilog -icells <<EOT
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module top(input C, E, R, S, D, output [3:0] Q);
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$_DFFSRE_PPPP_ ff0 (.C(C), .E(E), .R(R), .S(S), .D(D), .Q(Q[0]));
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$_DFFSRE_NPPP_ ff1 (.C(C), .E(E), .R(R), .S(S), .D(D), .Q(Q[1]));
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$_DFFSRE_PNNN_ ff2 (.C(C), .E(E), .R(R), .S(S), .D(D), .Q(Q[2]));
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$_DFFSRE_NNNN_ ff3 (.C(C), .E(E), .R(R), .S(S), .D(D), .Q(Q[3]));
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endmodule
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EOT
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equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_NNNN_ x -cell $_DFFSRE_PPPP_ x
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design -load postopt
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select -assert-count 6 t:$_NOT_
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select -assert-count 2 t:$_DFFSRE_PPPP_
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select -assert-count 2 t:$_DFFSRE_NNNN_
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select -assert-count 1 t:$_DFFSRE_PPPP_ n:ff0 %i
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select -assert-count 1 t:$_DFFSRE_NNNN_ n:ff1 %i
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select -assert-count 1 t:$_DFFSRE_PPPP_ n:ff2 %i
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select -assert-count 1 t:$_DFFSRE_NNNN_ n:ff3 %i
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