mirror of https://github.com/YosysHQ/yosys.git
32 lines
366 B
Verilog
32 lines
366 B
Verilog
module test_specify(input A, output B);
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specparam a=1;
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specify
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endspecify
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specify
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(A => B) = ( 1 ) ;
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(A- => B) = ( 1,2 ) ;
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(A+ => B) = ( 1,2,3 ) ;
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(A => B) = (
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1.1, 2, 3,
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4, 5.5, 6.6
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) ;
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(A => B) = (
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1.1, 2, 3,
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4, 5.5, 6.6 ,
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7.7, 8.8, 9,
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10.1, 11, 12
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) ;
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specparam b=1;
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specparam [1:2] asasa=1;
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endspecify
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specify
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specparam c=1:2:3;
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endspecify
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endmodule
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