mirror of https://github.com/YosysHQ/yosys.git
34 lines
725 B
Verilog
34 lines
725 B
Verilog
module demo_001(y1, y2, y3, y4);
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output [7:0] y1, y2, y3, y4;
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localparam [7:0] p1 = 123.45;
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localparam real p2 = 123.45;
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localparam real p3 = 123;
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localparam p4 = 123.45;
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assign y1 = p1 + 0.2;
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assign y2 = p2 + 0.2;
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assign y3 = p3 + 0.2;
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assign y4 = p4 + 0.2;
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endmodule
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module demo_002(y0, y1, y2, y3);
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output [63:0] y0, y1, y2, y3;
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assign y0 = 1'bx >= (-1 * -1.17);
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assign y1 = 1 ? 1 ? -1 : 'd0 : 0.0;
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assign y2 = 1 ? -1 : 1 ? 'd0 : 0.0;
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assign y3 = 1 ? -1 : 'd0;
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endmodule
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module demo_003(output A, B);
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parameter real p = 0;
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assign A = (p==1.0);
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assign B = (p!="1.000000");
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endmodule
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module demo_004(output A, B, C, D);
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demo_003 #(1.0) demo_real (A, B);
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demo_003 #(1) demo_int (C, D);
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endmodule
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