mirror of https://github.com/YosysHQ/yosys.git
28 lines
402 B
Verilog
28 lines
402 B
Verilog
`default_nettype none
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module named_genblk_top;
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generate
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if (1) begin
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wire t;
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begin : foo
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wire x;
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end
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wire u;
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end
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begin : bar
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wire x;
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wire y;
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begin : baz
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wire x;
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wire z;
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end
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end
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endgenerate
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assign genblk1.t = 1;
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assign genblk1.foo.x = 1;
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assign genblk1.u = 1;
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assign bar.x = 1;
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assign bar.y = 1;
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assign bar.baz.x = 1;
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assign bar.baz.z = 1;
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endmodule
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