mirror of https://github.com/YosysHQ/yosys.git
80 lines
2.1 KiB
Verilog
80 lines
2.1 KiB
Verilog
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// a simple test case extracted from systemcaes (as included in iwls2005)
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// this design has latches (or logic loops) for the two temp variables.
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// this latches (or logic loops) must be removed in the final synthesis results
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module aes(
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// inputs
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input [3:0] addroundkey_data_i,
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input [3:0] addroundkey_data_reg,
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input [3:0] addroundkey_round,
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input [3:0] key_i,
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input [3:0] keysched_new_key_o,
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input [3:0] round,
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input addroundkey_start_i,
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input keysched_ready_o,
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// outputs
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output reg [3:0] keysched_last_key_i,
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output reg [3:0] keysched_round_i,
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output reg [3:0] next_addroundkey_data_reg,
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output reg [3:0] next_addroundkey_round,
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output reg [3:0] round_data_var,
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output reg keysched_start_i,
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output reg next_addroundkey_ready_o
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);
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// temp variables
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reg [3:0] data_var;
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reg [3:0] round_key_var;
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always @*
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begin
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keysched_start_i = 0;
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keysched_round_i = addroundkey_round;
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round_data_var = addroundkey_data_reg;
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next_addroundkey_data_reg = addroundkey_data_reg;
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next_addroundkey_ready_o = 0;
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next_addroundkey_round = addroundkey_round;
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if (addroundkey_round == 1 || addroundkey_round == 0)
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keysched_last_key_i = key_i;
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else
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keysched_last_key_i = keysched_new_key_o;
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if (round == 0 && addroundkey_start_i)
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begin
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data_var = addroundkey_data_i;
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round_key_var = key_i;
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round_data_var = round_key_var ^ data_var;
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next_addroundkey_data_reg = round_data_var;
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next_addroundkey_ready_o = 1;
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end
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else if (addroundkey_start_i && round != 0)
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begin
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keysched_last_key_i = key_i;
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keysched_start_i = 1;
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keysched_round_i = 1;
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next_addroundkey_round = 1;
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end
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else if (addroundkey_round != round && keysched_ready_o)
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begin
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next_addroundkey_round = addroundkey_round + 1;
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keysched_last_key_i = keysched_new_key_o;
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keysched_start_i = 1;
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keysched_round_i = addroundkey_round + 1;
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end
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else if (addroundkey_round == round && keysched_ready_o)
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begin
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data_var = addroundkey_data_i;
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round_key_var = keysched_new_key_o;
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round_data_var = round_key_var ^ data_var;
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next_addroundkey_data_reg = round_data_var;
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next_addroundkey_ready_o = 1;
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next_addroundkey_round = 0;
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end
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end
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endmodule
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