mirror of https://github.com/YosysHQ/yosys.git
42 lines
962 B
Verilog
42 lines
962 B
Verilog
module func_width_scope_top(inp, out1, out2);
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input wire signed inp;
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localparam WIDTH_A = 5;
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function automatic [WIDTH_A-1:0] func1;
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input reg [WIDTH_A-1:0] inp;
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func1 = ~inp;
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endfunction
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wire [func1(0)-1:0] xc;
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assign xc = 1'sb1;
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wire [WIDTH_A-1:0] xn;
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assign xn = func1(inp);
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generate
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if (1) begin : blk
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localparam WIDTH_A = 6;
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function automatic [WIDTH_A-1:0] func2;
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input reg [WIDTH_A-1:0] inp;
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func2 = ~inp;
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endfunction
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wire [func2(0)-1:0] yc;
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assign yc = 1'sb1;
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wire [WIDTH_A-1:0] yn;
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assign yn = func2(inp);
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localparam WIDTH_B = 7;
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function automatic [WIDTH_B-1:0] func3;
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input reg [WIDTH_B-1:0] inp;
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func3 = ~inp;
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endfunction
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wire [func3(0)-1:0] zc;
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assign zc = 1'sb1;
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wire [WIDTH_B-1:0] zn;
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assign zn = func3(inp);
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end
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endgenerate
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output wire [1023:0] out1, out2;
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assign out1 = {xc, 1'b0, blk.yc, 1'b0, blk.zc};
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assign out2 = {xn, 1'b0, blk.yn, 1'b0, blk.zn};
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endmodule
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