mirror of https://github.com/YosysHQ/yosys.git
67 lines
3.5 KiB
Plaintext
67 lines
3.5 KiB
Plaintext
read_verilog -icells <<EOT
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module top(input clk, d, s, r, output reg [17:0] q);
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always @(posedge clk or posedge s) if ( s) q[ 0] <= 1'b1; else q[ 0] <= d;
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always @(posedge clk or negedge s) if (!s) q[ 1] <= 1'b1; else q[ 1] <= d;
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always @(posedge clk or posedge r) if ( r) q[ 2] <= 1'b0; else q[ 2] <= d;
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always @(posedge clk or negedge r) if (!r) q[ 3] <= 1'b0; else q[ 3] <= d;
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always @(negedge clk or posedge s) if ( s) q[ 4] <= 1'b1; else q[ 4] <= d;
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always @(negedge clk or negedge s) if (!s) q[ 5] <= 1'b1; else q[ 5] <= d;
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always @(negedge clk or posedge r) if ( r) q[ 6] <= 1'b0; else q[ 6] <= d;
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always @(negedge clk or negedge r) if (!r) q[ 7] <= 1'b0; else q[ 7] <= d;
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// Seems like proc_dlatch always sets {SET,CLR}_POLARITY to true
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always @(posedge clk or posedge s or posedge r) if ( r) q[ 8] <= 1'b0; else if ( s) q[ 8] <= 1'b1; else q[ 8] <= d;
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//always @(posedge clk or posedge s or negedge r) if (!r) q[ 9] <= 1'b0; else if ( s) q[ 9] <= 1'b1; else q[ 9] <= d;
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//always @(posedge clk or negedge s or posedge r) if ( r) q[10] <= 1'b0; else if (!s) q[10] <= 1'b1; else q[10] <= d;
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//always @(posedge clk or negedge s or negedge r) if (!r) q[11] <= 1'b0; else if (!s) q[11] <= 1'b1; else q[11] <= d;
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$dffsr #(.CLK_POLARITY(1'h1), .CLR_POLARITY(1'h0), .SET_POLARITY(1'h1), .WIDTH(32'd1)) ppn (.CLK(clk), .CLR(r), .D(d), .Q(q[ 9]), .SET(s));
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$dffsr #(.CLK_POLARITY(1'h1), .CLR_POLARITY(1'h1), .SET_POLARITY(1'h0), .WIDTH(32'd1)) pnp (.CLK(clk), .CLR(r), .D(d), .Q(q[10]), .SET(s));
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$dffsr #(.CLK_POLARITY(1'h1), .CLR_POLARITY(1'h0), .SET_POLARITY(1'h0), .WIDTH(32'd1)) pnn (.CLK(clk), .CLR(r), .D(d), .Q(q[11]), .SET(s));
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always @(negedge clk or posedge s or posedge r) if ( r) q[12] <= 1'b0; else if ( s) q[12] <= 1'b1; else q[12] <= d;
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//always @(negedge clk or posedge s or negedge r) if (!r) q[13] <= 1'b0; else if ( s) q[13] <= 1'b1; else q[13] <= d;
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//always @(negedge clk or negedge s or posedge r) if ( r) q[14] <= 1'b0; else if (!s) q[14] <= 1'b1; else q[14] <= d;
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//always @(negedge clk or negedge s or negedge r) if (!r) q[15] <= 1'b0; else if (!s) q[15] <= 1'b1; else q[15] <= d;
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$dffsr #(.CLK_POLARITY(1'h0), .CLR_POLARITY(1'h0), .SET_POLARITY(1'h1), .WIDTH(32'd1)) npn (.CLK(clk), .CLR(r), .D(d), .Q(q[13]), .SET(s));
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$dffsr #(.CLK_POLARITY(1'h0), .CLR_POLARITY(1'h1), .SET_POLARITY(1'h0), .WIDTH(32'd1)) nnp (.CLK(clk), .CLR(r), .D(d), .Q(q[14]), .SET(s));
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$dffsr #(.CLK_POLARITY(1'h0), .CLR_POLARITY(1'h0), .SET_POLARITY(1'h0), .WIDTH(32'd1)) nnn (.CLK(clk), .CLR(r), .D(d), .Q(q[15]), .SET(s));
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always @(posedge clk) q[16] <= d;
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always @(negedge clk) q[17] <= d;
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endmodule
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EOT
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proc
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select -assert-count 8 t:$adff
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select -assert-count 8 t:$dffsr
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select -assert-count 2 t:$dff
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design -save gold
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simplemap
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select -assert-count 1 t:$_DFF_NN0_
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select -assert-count 1 t:$_DFF_NN1_
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select -assert-count 1 t:$_DFF_NP0_
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select -assert-count 1 t:$_DFF_NP1_
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select -assert-count 1 t:$_DFF_PN0_
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select -assert-count 1 t:$_DFF_PN1_
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select -assert-count 1 t:$_DFF_PP0_
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select -assert-count 1 t:$_DFF_PP1_
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stat
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select -assert-count 1 t:$_DFFSR_NNN_
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select -assert-count 1 t:$_DFFSR_NNP_
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select -assert-count 1 t:$_DFFSR_NPN_
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select -assert-count 1 t:$_DFFSR_NPP_
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select -assert-count 1 t:$_DFFSR_PNN_
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select -assert-count 1 t:$_DFFSR_PNP_
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select -assert-count 1 t:$_DFFSR_PPN_
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select -assert-count 1 t:$_DFFSR_PPP_
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select -assert-count 1 t:$_DFF_N_
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select -assert-count 1 t:$_DFF_P_
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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clk2fflogic
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports -set-init-undef -seq 10 miter
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