mirror of https://github.com/YosysHQ/yosys.git
80 lines
2.0 KiB
Verilog
80 lines
2.0 KiB
Verilog
module alu(
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input clk,
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input [7:0] A,
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input [7:0] B,
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input [3:0] operation,
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output reg [7:0] result,
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output reg CF,
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output reg ZF,
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output reg SF
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);
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localparam ALU_OP_ADD /* verilator public_flat */ = 4'b0000;
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localparam ALU_OP_SUB /* verilator public_flat */ = 4'b0001;
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localparam ALU_OP_ADC /* verilator public_flat */ = 4'b0010;
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localparam ALU_OP_SBC /* verilator public_flat */ = 4'b0011;
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localparam ALU_OP_AND /* verilator public_flat */ = 4'b0100;
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localparam ALU_OP_OR /* verilator public_flat */ = 4'b0101;
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localparam ALU_OP_NOT /* verilator public_flat */ = 4'b0110;
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localparam ALU_OP_XOR /* verilator public_flat */ = 4'b0111;
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localparam ALU_OP_SHL /* verilator public_flat */ = 4'b1000;
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localparam ALU_OP_SHR /* verilator public_flat */ = 4'b1001;
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localparam ALU_OP_SAL /* verilator public_flat */ = 4'b1010;
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localparam ALU_OP_SAR /* verilator public_flat */ = 4'b1011;
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localparam ALU_OP_ROL /* verilator public_flat */ = 4'b1100;
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localparam ALU_OP_ROR /* verilator public_flat */ = 4'b1101;
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localparam ALU_OP_RCL /* verilator public_flat */ = 4'b1110;
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localparam ALU_OP_RCR /* verilator public_flat */ = 4'b1111;
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reg [8:0] tmp;
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always @(posedge clk)
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begin
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case (operation)
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ALU_OP_ADD :
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tmp = A + B;
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ALU_OP_SUB :
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tmp = A - B;
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ALU_OP_ADC :
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tmp = A + B + { 7'b0000000, CF };
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ALU_OP_SBC :
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tmp = A - B - { 7'b0000000, CF };
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ALU_OP_AND :
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tmp = {1'b0, A & B };
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ALU_OP_OR :
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tmp = {1'b0, A | B };
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ALU_OP_NOT :
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tmp = {1'b0, ~B };
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ALU_OP_XOR :
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tmp = {1'b0, A ^ B};
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ALU_OP_SHL :
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tmp = { A[7], A[6:0], 1'b0};
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ALU_OP_SHR :
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tmp = { A[0], 1'b0, A[7:1]};
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ALU_OP_SAL :
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// Same as SHL
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tmp = { A[7], A[6:0], 1'b0};
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ALU_OP_SAR :
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tmp = { A[0], A[7], A[7:1]};
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ALU_OP_ROL :
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tmp = { A[7], A[6:0], A[7]};
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ALU_OP_ROR :
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tmp = { A[0], A[0], A[7:1]};
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ALU_OP_RCL :
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tmp = { A[7], A[6:0], CF};
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ALU_OP_RCR :
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tmp = { A[0], CF, A[7:1]};
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endcase
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CF <= tmp[8];
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ZF <= tmp[7:0] == 0;
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SF <= tmp[7];
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result <= tmp[7:0];
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end
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endmodule
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