mirror of https://github.com/YosysHQ/yosys.git
14 lines
354 B
Plaintext
14 lines
354 B
Plaintext
read_verilog opt_share_diff_port_widths.v
|
|
proc;;
|
|
copy opt_share_test merged
|
|
|
|
alumacc merged
|
|
opt merged
|
|
opt_share merged
|
|
opt_clean merged
|
|
|
|
miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp opt_share_test merged miter
|
|
sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter
|
|
|
|
select -assert-count 2 -module merged t:$alu
|