mirror of https://github.com/YosysHQ/yosys.git
92 lines
1.4 KiB
Plaintext
92 lines
1.4 KiB
Plaintext
read_rtlil << EOT
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module \top
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wire width 4 input 0 \A
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wire width 2 input 1 \S
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wire width 24 output 2 \Y
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cell $demux $0
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parameter \WIDTH 6
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parameter \S_WIDTH 2
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connect \A { \A [3] \A [1] 1'0 \A [2:0] }
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connect \S \S
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connect \Y \Y
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end
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end
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EOT
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equiv_opt -assert opt_reduce -fine
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opt_reduce -fine
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select -assert-count 1 t:$demux r:WIDTH=4 %i
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design -reset
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read_rtlil << EOT
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module \top
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wire width 2 input 1 \S
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wire width 24 output 2 \Y
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cell $demux $0
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parameter \WIDTH 6
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parameter \S_WIDTH 2
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connect \A 6'000000
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connect \S \S
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connect \Y \Y
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end
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end
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EOT
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equiv_opt -assert opt_reduce -fine
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opt_reduce -fine
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select -assert-count 0 t:$demux
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design -reset
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read_rtlil << EOT
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module \top
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wire width 5 input 0 \A
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wire width 2 input 1 \S
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wire width 160 output 2 \Y
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cell $demux $0
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parameter \WIDTH 5
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parameter \S_WIDTH 5
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connect \A \A
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connect \S { \S [0] \S [1] 1'1 \S [0] 1'0 }
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connect \Y \Y
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end
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end
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EOT
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equiv_opt -assert opt_reduce -fine
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opt_reduce -fine
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select -assert-count 1 t:$demux r:S_WIDTH=2 %i
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design -reset
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read_rtlil << EOT
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module \top
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wire width 5 input 0 \A
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wire width 20 output 2 \Y
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cell $demux $0
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parameter \WIDTH 5
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parameter \S_WIDTH 2
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connect \A \A
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connect \S { 2'10 }
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connect \Y \Y
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end
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end
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EOT
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equiv_opt -assert opt_reduce -fine
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opt_reduce -fine
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select -assert-count 0 t:$demux
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