mirror of https://github.com/YosysHQ/yosys.git
118 lines
1.9 KiB
Plaintext
118 lines
1.9 KiB
Plaintext
read_rtlil << EOT
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module \top
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wire width 12 input 0 \A
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wire width 2 input 1 \S
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wire width 6 output 2 \Y
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cell $bmux $0
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parameter \WIDTH 6
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parameter \S_WIDTH 2
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connect \A { \A [11:10] \A [3:2] \A [10:9] \A [7] \A [7] \A [8] \A [2] \A [7:6] \A [5] \A [5] \A [3:2] \A [5:4] \A [1] \A [1] \A [3:0] }
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connect \S \S
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connect \Y \Y
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end
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end
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EOT
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equiv_opt -assert opt_reduce -fine
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opt_reduce -fine
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select -assert-count 1 t:$bmux r:WIDTH=4 %i
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design -reset
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read_rtlil << EOT
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module \top
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wire width 6 input 0 \A
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wire width 2 input 1 \S
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wire width 6 output 2 \Y
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cell $bmux $0
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parameter \WIDTH 6
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parameter \S_WIDTH 2
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connect \A { \A [5:0] \A [5:0] \A [5:0] \A [5:0] }
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connect \S \S
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connect \Y \Y
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end
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end
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EOT
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equiv_opt -assert opt_reduce -fine
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opt_reduce -fine
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select -assert-count 0 t:$bmux
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design -reset
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read_rtlil << EOT
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module \top
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wire width 160 input 0 \A
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wire width 2 input 1 \S
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wire width 5 output 2 \Y
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cell $bmux $0
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parameter \WIDTH 5
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parameter \S_WIDTH 5
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connect \A \A
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connect \S { \S [1] 1'1 \S [0] \S [1] 1'0 }
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connect \Y \Y
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end
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end
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EOT
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equiv_opt -assert opt_reduce -fine
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opt_reduce -fine
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select -assert-count 1 t:$bmux r:S_WIDTH=2 %i
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design -reset
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read_rtlil << EOT
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module \top
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wire width 10 input 0 \A
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wire input 1 \S
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wire width 5 output 2 \Y
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cell $bmux $0
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parameter \WIDTH 5
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parameter \S_WIDTH 1
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connect \A \A
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connect \S \S
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connect \Y \Y
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end
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end
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EOT
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equiv_opt -assert opt_reduce -fine
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opt_reduce -fine
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select -assert-count 0 t:$bmux
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select -assert-count 1 t:$mux
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design -reset
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read_rtlil << EOT
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module \top
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wire width 5 input 0 \A
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wire width 5 output 1 \Y
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cell $bmux $0
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parameter \WIDTH 5
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parameter \S_WIDTH 0
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connect \A \A
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connect \S { }
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connect \Y \Y
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end
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end
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EOT
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equiv_opt -assert opt_reduce -fine
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opt_reduce -fine
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select -assert-count 0 t:$bmux
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