mirror of https://github.com/YosysHQ/yosys.git
128 lines
1.9 KiB
Plaintext
128 lines
1.9 KiB
Plaintext
read_verilog -icells <<EOT
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module top(input clk, i, (* init = 1'b0 *) output o, p);
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\$dff #(
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.CLK_POLARITY(1'h1),
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.WIDTH(32'd1)
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) ffo (
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.CLK(clk),
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.D(i),
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.Q(o)
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);
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\$dff #(
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.CLK_POLARITY(1'h1),
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.WIDTH(32'd1)
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) ffp (
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.CLK(clk),
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.D(i),
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.Q(p)
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);
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endmodule
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EOT
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opt_merge
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select -assert-count 1 t:$dff
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select -assert-count 1 a:init=1'0
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design -reset
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read_verilog -icells <<EOT
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module top(input clk, i, (* init = 2'b11 *) output [1:0] o);
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\$dff #(
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.CLK_POLARITY(1'h1),
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.WIDTH(32'd1)
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) ff1 (
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.CLK(clk),
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.D(i),
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.Q(o[1])
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);
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\$dff #(
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.CLK_POLARITY(1'h1),
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.WIDTH(32'd1)
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) ff0 (
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.CLK(clk),
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.D(i),
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.Q(o[0])
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);
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endmodule
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EOT
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opt_merge
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select -assert-count 1 t:$dff
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select -assert-count 1 a:init=2'bx1 a:init=2'b1x
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design -reset
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read_verilog -icells <<EOT
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module top(input clk, i, (* init = 1'b0 *) output o, /* NB: no init here! */ output p);
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\$dff #(
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.CLK_POLARITY(1'h1),
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.WIDTH(32'd1)
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) ffo (
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.CLK(clk),
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.D(i),
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.Q(o)
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);
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\$dff #(
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.CLK_POLARITY(1'h1),
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.WIDTH(32'd1)
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) ffp (
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.CLK(clk),
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.D(i),
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.Q(p)
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);
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endmodule
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EOT
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opt_merge
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select -assert-count 2 t:$dff
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design -reset
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read_verilog -icells <<EOT
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module top(input clk, i, (* init = 1'b0 *) output o, p);
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\$dff #(
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.CLK_POLARITY(1'h1),
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.WIDTH(32'd1)
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) ffo (
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.CLK(clk),
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.D(i),
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.Q(o)
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);
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\$dff #(
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.CLK_POLARITY(1'h1),
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.WIDTH(32'd1)
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) ffp (
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.CLK(clk),
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.D(i),
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.Q(p)
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);
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endmodule
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EOT
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opt_merge -keepdc
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select -assert-count 1 t:$dff
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design -reset
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read_verilog -icells <<EOT
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module top(input clk, i, output o, p);
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\$dff #(
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.CLK_POLARITY(1'h1),
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.WIDTH(32'd1)
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) ffo (
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.CLK(clk),
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.D(i),
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.Q(o)
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);
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\$dff #(
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.CLK_POLARITY(1'h1),
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.WIDTH(32'd1)
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) ffp (
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.CLK(clk),
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.D(i),
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.Q(p)
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);
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endmodule
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EOT
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opt_merge -keepdc
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select -assert-count 2 t:$dff
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