mirror of https://github.com/YosysHQ/yosys.git
419 lines
7.7 KiB
Verilog
419 lines
7.7 KiB
Verilog
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// test_intermout_always_comb_1_test.v
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module f1_test(a, b, c, d, z);
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input a, b, c, d;
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output z;
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reg z, temp1, temp2;
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always @(a or b or c or d)
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begin
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temp1 = a ^ b;
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temp2 = c ^ d;
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z = temp1 ^ temp2;
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end
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endmodule
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// test_intermout_always_comb_3_test.v
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module f2_test (in1, in2, out);
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input in1, in2;
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output reg out;
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always @ ( in1 or in2)
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if(in1 > in2)
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out = in1;
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else
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out = in2;
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endmodule
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// test_intermout_always_comb_4_test.v
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module f3_test(a, b, c);
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input b, c;
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output reg a;
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always @(b or c) begin
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a = b;
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a = c;
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end
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endmodule
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// test_intermout_always_comb_5_test.v
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module f4_test(ctrl, in1, in2, out);
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input ctrl;
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input in1, in2;
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output reg out;
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always @ (ctrl or in1 or in2)
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if(ctrl)
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out = in1 & in2;
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else
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out = in1 | in2;
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endmodule
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// test_intermout_always_ff_3_test.v
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module f5_NonBlockingEx(clk, merge, er, xmit, fddi, claim);
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input clk, merge, er, xmit, fddi;
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output reg claim;
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reg fcr;
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always @(posedge clk)
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begin
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fcr = er | xmit;
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if(merge)
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claim = fcr & fddi;
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else
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claim = fddi;
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end
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endmodule
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// test_intermout_always_ff_4_test.v
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module f6_FlipFlop(clk, cs, ns);
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input clk;
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input [31:0] cs;
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output [31:0] ns;
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integer is;
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always @(posedge clk)
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is <= cs;
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assign ns = is;
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endmodule
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// test_intermout_always_ff_5_test.v
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module f7_FlipFlop(clock, cs, ns);
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input clock;
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input [3:0] cs;
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output reg [3:0] ns;
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reg [3:0] temp;
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always @(posedge clock)
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begin
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temp = cs;
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ns = temp;
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end
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endmodule
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// test_intermout_always_ff_6_test.v
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module f8_inc(clock, counter);
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input clock;
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output reg [3:0] counter;
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always @(posedge clock)
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counter <= counter + 1;
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endmodule
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// test_intermout_always_ff_8_test.v
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module f9_NegEdgeClock(q, d, clk, reset);
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input d, clk, reset;
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output reg q;
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always @(negedge clk or negedge reset)
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if(!reset)
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q <= 1'b0;
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else
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q <= d;
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endmodule
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// test_intermout_always_ff_9_test.v
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module f10_MyCounter (clock, preset, updown, presetdata, counter);
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input clock, preset, updown;
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input [1: 0] presetdata;
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output reg [1:0] counter;
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always @(posedge clock)
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if(preset)
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counter <= presetdata;
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else
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if(updown)
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counter <= counter + 1;
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else
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counter <= counter - 1;
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endmodule
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// test_intermout_always_latch_1_test.v
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module f11_test(en, in, out);
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input en;
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input [1:0] in;
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output reg [2:0] out;
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always @ (en or in)
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if(en)
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out = in + 1;
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endmodule
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// test_intermout_bufrm_1_test.v
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module f12_test(input in, output out);
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//no buffer removal
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assign out = in;
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endmodule
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// test_intermout_bufrm_2_test.v
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module f13_test(input in, output out);
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//intermediate buffers should be removed
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wire w1, w2;
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assign w1 = in;
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assign w2 = w1;
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assign out = w2;
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endmodule
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// test_intermout_bufrm_6_test.v
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module f14_test(in, out);
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input in;
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output out;
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wire w1, w2, w3, w4;
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assign w1 = in;
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assign w2 = w1;
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assign w4 = w3;
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assign out = w4;
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f14_mybuf _f14_mybuf(w2, w3);
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endmodule
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module f14_mybuf(in, out);
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input in;
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output out;
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wire w1, w2, w3, w4;
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assign w1 = in;
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assign w2 = w1;
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assign out = w2;
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endmodule
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// test_intermout_bufrm_7_test.v
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module f15_test(in1, in2, out);
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input in1, in2;
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output out;
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// Y with cluster of f15_mybuf instances at the junction
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wire w1, w2, w3, w4, w5, w6, w7, w8, w9, w10;
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assign w1 = in1;
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assign w2 = w1;
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assign w5 = in2;
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assign w6 = w5;
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assign w10 = w9;
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assign out = w10;
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f15_mybuf _f15_mybuf0(w2, w3);
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f15_mybuf _f15_mybuf1(w3, w4);
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f15_mybuf _f15_mybuf2(w6, w7);
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f15_mybuf _f15_mybuf3(w7, w4);
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f15_mybuf _f15_mybuf4(w4, w8);
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f15_mybuf _f15_mybuf5(w8, w9);
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endmodule
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module f15_mybuf(in, out);
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input in;
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output out;
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wire w1, w2, w3, w4;
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assign w1 = in;
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assign w2 = w1;
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assign out = w2;
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endmodule
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// test_intermout_exprs_add_test.v
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module f16_test(out, in1, in2, vin1, vin2, vout1);
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output out;
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input in1, in2;
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input [1:0] vin1;
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input [2:0] vin2;
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output [3:0] vout1;
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assign out = in1 + in2;
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assign vout1 = vin1 + vin2;
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endmodule
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// test_intermout_exprs_binlogic_test.v
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module f17_test(in1, in2, vin1, vin2, out, vout, vin3, vin4, vout1 );
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input in1, in2;
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input [1:0] vin1;
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input [3:0] vin2;
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input [1:0] vin3;
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input [3:0] vin4;
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output vout, vout1;
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output out;
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assign out = in1 && in2;
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assign vout = vin1 && vin2;
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assign vout1 = vin3 || vin4;
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endmodule
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// test_intermout_exprs_bitwiseneg_test.v
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module f18_test(output out, input in, output [1:0] vout, input [1:0] vin);
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assign out = ~in;
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assign vout = ~vin;
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endmodule
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// test_intermout_exprs_buffer_test.v
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module f19_buffer(in, out, vin, vout);
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input in;
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output out;
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input [1:0] vin;
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output [1:0] vout;
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assign out = in;
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assign vout = vin;
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endmodule
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// test_intermout_exprs_condexpr_mux_test.v
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module f20_test(in1, in2, out, vin1, vin2, vin3, vin4, vout1, vout2, en1, ven1, ven2);
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input in1, in2, en1, ven1;
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input [1:0] ven2;
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output out;
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input [1:0] vin1, vin2, vin3, vin4;
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output [1:0] vout1, vout2;
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assign out = en1 ? in1 : in2;
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assign vout1 = ven1 ? vin1 : vin2;
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assign vout2 = ven2 ? vin3 : vin4;
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endmodule
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// test_intermout_exprs_condexpr_tribuf_test.v
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module f21_test(in, out, en, vin1, vout1, en1);
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input in, en, en1;
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output out;
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input [1:0] vin1;
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output [1:0] vout1;
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assign out = en ? in : 1'bz;
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assign vout1 = en1 ? vin1 : 2'bzz;
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endmodule
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// test_intermout_exprs_constshift_test.v
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module f22_test(in, out, vin, vout, vin1, vout1, vin2, vout2);
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input in;
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input [3:0] vin, vin1, vin2;
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output [3:0] vout, vout1, vout2;
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output out;
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assign out = in << 1;
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assign vout = vin << 2;
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assign vout1 = vin1 >> 2;
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assign vout2 = vin2 >>> 2;
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endmodule
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// test_intermout_exprs_const_test.v
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module f23_test (out, vout);
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output out;
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output [7:0] vout;
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assign out = 1'b1;
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assign vout = 9;
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endmodule
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// test_intermout_exprs_div_test.v
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module f24_test(out, in1, in2, vin1, vin2, vout1);
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output out;
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input in1, in2;
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input [1:0] vin1;
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input [2:0] vin2;
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output [3:0] vout1;
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assign out = in1 / in2;
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assign vout1 = vin1 / vin2;
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endmodule
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// test_intermout_exprs_logicneg_test.v
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module f25_test(out, vout, in, vin);
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output out, vout;
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input in;
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input [3:0] vin;
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assign out = !in;
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assign vout = !vin;
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endmodule
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// test_intermout_exprs_mod_test.v
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module f26_test(out, in1, in2, vin1, vin2, vout1);
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output out;
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input in1, in2;
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input [1:0] vin1;
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input [2:0] vin2;
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output [3:0] vout1;
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assign out = in1 % in2;
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assign vout1 = vin1 % vin2;
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endmodule
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// test_intermout_exprs_mul_test.v
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module f27_test(out, in1, in2, vin1, vin2, vout1);
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output out;
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input in1, in2;
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input [1:0] vin1;
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input [2:0] vin2;
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output [3:0] vout1;
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assign out = in1 * in2;
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assign vout1 = vin1 * vin2;
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endmodule
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// test_intermout_exprs_redand_test.v
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module f28_test(output out, input [1:0] vin, output out1, input [3:0] vin1);
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assign out = &vin;
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assign out1 = &vin1;
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endmodule
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// test_intermout_exprs_redop_test.v
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module f29_Reduction (A1, A2, A3, A4, A5, A6, Y1, Y2, Y3, Y4, Y5, Y6);
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input [1:0] A1;
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input [1:0] A2;
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input [1:0] A3;
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input [1:0] A4;
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input [1:0] A5;
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input [1:0] A6;
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output Y1, Y2, Y3, Y4, Y5, Y6;
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//reg Y1, Y2, Y3, Y4, Y5, Y6;
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assign Y1=&A1; //reduction AND
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assign Y2=|A2; //reduction OR
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assign Y3=~&A3; //reduction NAND
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assign Y4=~|A4; //reduction NOR
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assign Y5=^A5; //reduction XOR
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assign Y6=~^A6; //reduction XNOR
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endmodule
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// test_intermout_exprs_sub_test.v
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module f30_test(out, in1, in2, vin1, vin2, vout1);
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output out;
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input in1, in2;
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input [1:0] vin1;
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input [2:0] vin2;
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output [3:0] vout1;
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assign out = in1 - in2;
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assign vout1 = vin1 - vin2;
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endmodule
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// test_intermout_exprs_unaryminus_test.v
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module f31_test(output out, input in, output [31:0] vout, input [31:0] vin);
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assign out = -in;
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assign vout = -vin;
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endmodule
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// test_intermout_exprs_unaryplus_test.v
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module f32_test(output out, input in);
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assign out = +in;
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endmodule
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// test_intermout_exprs_varshift_test.v
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module f33_test(vin0, vout0);
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input [2:0] vin0;
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output reg [7:0] vout0;
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wire [7:0] myreg0, myreg1, myreg2;
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integer i;
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assign myreg0 = vout0 << vin0;
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assign myreg1 = myreg2 >> i;
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endmodule
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