mirror of https://github.com/YosysHQ/yosys.git
95 lines
4.5 KiB
Python
95 lines
4.5 KiB
Python
import subprocess
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import pytest
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import sys
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import shlex
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from pathlib import Path
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base_path = Path(__file__).resolve().parent.parent.parent
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# quote a string or pathlib path so that it can be used by bash or yosys
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# TODO: is this really appropriate for yosys?
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def quote(path):
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return shlex.quote(str(path))
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# run a shell command and require the return code to be 0
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def run(cmd, **kwargs):
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print(' '.join([quote(x) for x in cmd]))
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status = subprocess.run(cmd, **kwargs)
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assert status.returncode == 0, f"{cmd[0]} failed"
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def yosys(script):
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run([base_path / 'yosys', '-Q', '-p', script])
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def compile_cpp(in_path, out_path, args):
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run(['g++', '-g', '-std=c++17'] + args + [str(in_path), '-o', str(out_path)])
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def yosys_synth(verilog_file, rtlil_file):
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yosys(f"read_verilog {quote(verilog_file)} ; prep ; write_rtlil {quote(rtlil_file)}")
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# simulate an rtlil file with yosys, comparing with a given vcd file, and writing out the yosys simulation results into a second vcd file
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def yosys_sim(rtlil_file, vcd_reference_file, vcd_out_file, preprocessing = ""):
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try:
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yosys(f"read_rtlil {quote(rtlil_file)}; {preprocessing}; sim -r {quote(vcd_reference_file)} -scope gold -vcd {quote(vcd_out_file)} -timescale 1us -sim-gold -fst-noinit")
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except:
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# if yosys sim fails it's probably because of a simulation mismatch
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# since yosys sim aborts on simulation mismatch to generate vcd output
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# we have to re-run with a different set of flags
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# on this run we ignore output and return code, we just want a best-effort attempt to get a vcd
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subprocess.run([base_path / 'yosys', '-Q', '-p',
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f'read_rtlil {quote(rtlil_file)}; sim -vcd {quote(vcd_out_file)} -a -r {quote(vcd_reference_file)} -scope gold -timescale 1us -fst-noinit'],
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capture_output=True, check=False)
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raise
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def test_cxx(cell, parameters, tmp_path, num_steps, rnd):
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rtlil_file = tmp_path / 'rtlil.il'
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vcdharness_cc_file = base_path / 'tests/functional/vcd_harness.cc'
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cc_file = tmp_path / 'my_module_functional_cxx.cc'
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vcdharness_exe_file = tmp_path / 'a.out'
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vcd_functional_file = tmp_path / 'functional.vcd'
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vcd_yosys_sim_file = tmp_path / 'yosys.vcd'
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cell.write_rtlil_file(rtlil_file, parameters)
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yosys(f"read_rtlil {quote(rtlil_file)} ; clk2fflogic ; write_functional_cxx {quote(cc_file)}")
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compile_cpp(vcdharness_cc_file, vcdharness_exe_file, ['-I', tmp_path, '-I', str(base_path / 'backends/functional/cxx_runtime')])
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seed = str(rnd(cell.name + "-cxx").getrandbits(32))
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run([str(vcdharness_exe_file.resolve()), str(vcd_functional_file), str(num_steps), str(seed)])
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yosys_sim(rtlil_file, vcd_functional_file, vcd_yosys_sim_file, getattr(cell, 'sim_preprocessing', ''))
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@pytest.mark.smt
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def test_smt(cell, parameters, tmp_path, num_steps, rnd):
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import smt_vcd
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rtlil_file = tmp_path / 'rtlil.il'
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smt_file = tmp_path / 'smtlib.smt'
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vcd_functional_file = tmp_path / 'functional.vcd'
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vcd_yosys_sim_file = tmp_path / 'yosys.vcd'
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if hasattr(cell, 'smt_max_steps'):
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num_steps = min(num_steps, cell.smt_max_steps)
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cell.write_rtlil_file(rtlil_file, parameters)
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yosys(f"read_rtlil {quote(rtlil_file)} ; clk2fflogic ; write_functional_smt2 {quote(smt_file)}")
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run(['z3', smt_file]) # check if output is valid smtlib before continuing
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smt_vcd.simulate_smt(smt_file, vcd_functional_file, num_steps, rnd(cell.name + "-smt"))
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yosys_sim(rtlil_file, vcd_functional_file, vcd_yosys_sim_file, getattr(cell, 'sim_preprocessing', ''))
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@pytest.mark.rkt
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def test_rkt(cell, parameters, tmp_path, num_steps, rnd):
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import rkt_vcd
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rtlil_file = tmp_path / 'rtlil.il'
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rkt_file = tmp_path / 'smtlib.rkt'
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vcd_functional_file = tmp_path / 'functional.vcd'
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vcd_yosys_sim_file = tmp_path / 'yosys.vcd'
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cell.write_rtlil_file(rtlil_file, parameters)
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yosys(f"read_rtlil {quote(rtlil_file)} ; clk2fflogic ; write_functional_rosette -provides {quote(rkt_file)}")
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rkt_vcd.simulate_rosette(rkt_file, vcd_functional_file, num_steps, rnd(cell.name + "-rkt"))
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yosys_sim(rtlil_file, vcd_functional_file, vcd_yosys_sim_file, getattr(cell, 'sim_preprocessing', ''))
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def test_print_graph(tmp_path):
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tb_file = base_path / 'tests/functional/picorv32_tb.v'
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cpu_file = base_path / 'tests/functional/picorv32.v'
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# currently we only check that we can print the graph without getting an error, not that it prints anything sensibl
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yosys(f"read_verilog {quote(tb_file)} {quote(cpu_file)}; prep -top gold; flatten; clk2fflogic; test_generic")
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