mirror of https://github.com/YosysHQ/yosys.git
116 lines
4.7 KiB
Python
116 lines
4.7 KiB
Python
from __future__ import annotations
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from pathlib import Path
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import re
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import subprocess
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from typing import Dict, List, Tuple
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from random import Random
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vcd_version = "Yosys/tests/functional/rkt_vcd.py"
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StepList = List[Tuple[int, str]]
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SignalStepMap = Dict[str, StepList]
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SignalWidthMap = Dict[str, int]
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def write_vcd(filename: Path, signals: SignalStepMap, timescale='1 ns', date='today'):
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with open(filename, 'w') as f:
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# Write the header
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f.write(f"$date\n {date}\n$end\n")
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f.write(f"$timescale {timescale} $end\n")
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# Declare signals
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f.write("$scope module gold $end\n")
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for signal_name, changes in signals.items():
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signal_size = len(changes[0][1])
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f.write(f"$var wire {signal_size - 1} {signal_name} {signal_name} $end\n")
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f.write("$upscope $end\n")
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f.write("$enddefinitions $end\n")
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# Collect all unique timestamps
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timestamps = sorted(set(time for changes in signals.values() for time, _ in changes))
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# Write initial values
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f.write("#0\n")
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for signal_name, changes in signals.items():
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for time, value in changes:
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if time == 0:
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f.write(f"{value} {signal_name}\n")
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# Write value changes
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for time in timestamps:
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if time != 0:
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f.write(f"#{time}\n")
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for signal_name, changes in signals.items():
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for change_time, value in changes:
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if change_time == time:
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f.write(f"{value} {signal_name}\n")
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def simulate_rosette(rkt_file_path: Path, vcd_path: Path, num_steps: int, rnd: Random):
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signals: dict[str, list[str]] = {}
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inputs: SignalWidthMap = {}
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outputs: SignalWidthMap = {}
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current_struct_name: str = ""
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with open(rkt_file_path, 'r') as rkt_file:
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for line in rkt_file:
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m = re.search(r'gold_(Inputs|Outputs|State)', line)
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if m:
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current_struct_name = m.group(1)
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if current_struct_name == "State": break
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elif not current_struct_name: continue # skip lines before structs
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m = re.search(r'; (.+?)\b \(bitvector (\d+)\)', line)
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if not m: continue # skip non matching lines (probably closing the struct)
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signal = m.group(1)
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width = int(m.group(2))
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if current_struct_name == "Inputs":
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inputs[signal] = width
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elif current_struct_name == "Outputs":
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outputs[signal] = width
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for signal, width in inputs.items():
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step_list: list[int] = []
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for step in range(num_steps):
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value = rnd.getrandbits(width)
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binary_string = format(value, '0{}b'.format(width))
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step_list.append(binary_string)
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signals[signal] = step_list
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test_rkt_file_path = rkt_file_path.with_suffix('.tst.rkt')
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with open(test_rkt_file_path, 'w') as test_rkt_file:
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test_rkt_file.writelines([
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'#lang rosette\n',
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f'(require "{rkt_file_path.name}")\n',
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])
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for step in range(num_steps):
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this_step = f"step_{step}"
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value_list: list[str] = []
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for signal, width in inputs.items():
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value = signals[signal][step]
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value_list.append(f"(bv #b{value} {width})")
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gold_Inputs = f"(gold_Inputs {' '.join(value_list)})"
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gold_State = f"(cdr step_{step-1})" if step else "gold_initial"
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test_rkt_file.write(f"(define {this_step} (gold {gold_Inputs} {gold_State})) (car {this_step})\n")
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cmd = ["racket", test_rkt_file_path]
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status = subprocess.run(cmd, capture_output=True)
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assert status.returncode == 0, f"{cmd[0]} failed"
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for signal in outputs.keys():
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signals[signal] = []
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for line in status.stdout.decode().splitlines():
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m = re.match(r'\(gold_Outputs( \(bv \S+ \d+\))+\)', line)
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assert m, f"Incomplete output definition {line!r}"
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for output, (value, width) in zip(outputs.keys(), re.findall(r'\(bv (\S+) (\d+)\)', line)):
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assert isinstance(value, str), f"Bad value {value!r}"
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assert value.startswith(('#b', '#x')), f"Non-binary value {value!r}"
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assert int(width) == outputs[output], f"Width mismatch for output {output!r} (got {width}, expected {outputs[output]})"
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int_value = int(value[2:], 16 if value.startswith('#x') else 2)
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binary_string = format(int_value, '0{}b'.format(width))
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signals[output].append(binary_string)
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vcd_signals: SignalStepMap = {}
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for signal, steps in signals.items():
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vcd_signals[signal] = [(time, f"b{value}") for time, value in enumerate(steps)]
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write_vcd(vcd_path, vcd_signals)
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