riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
yosys/tests/errors/syntax_err10.v

4 lines
48 B
Verilog
Raw Permalink Blame History

module a;
parameter integer [2:0]x=0;
endmodule
Reference in New Issue View Git Blame Copy Permalink