mirror of https://github.com/YosysHQ/yosys.git
13 lines
566 B
Bash
13 lines
566 B
Bash
#!/usr/bin/env bash
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set -e
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../../yosys -qq -f verilog -p "proc; opt; memory -nomap -bram temp/brams_${2}.txt; opt -fast -full" \
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-l temp/synth_${1}_${2}.log -o temp/synth_${1}_${2}.v temp/brams_${1}.v
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iverilog -Dvcd_file=\"temp/tb_${1}_${2}.vcd\" -DSIMLIB_MEMDELAY=1 -o temp/tb_${1}_${2}.tb temp/brams_${1}_tb.v \
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temp/brams_${1}_ref.v temp/synth_${1}_${2}.v temp/brams_${2}.v ../../techlibs/common/simlib.v
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temp/tb_${1}_${2}.tb > temp/tb_${1}_${2}.txt
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if grep -q ERROR temp/tb_${1}_${2}.txt; then
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grep -HC2 ERROR temp/tb_${1}_${2}.txt | head
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exit 1
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fi
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exit 0
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