mirror of https://github.com/YosysHQ/yosys.git
25 lines
512 B
Systemverilog
25 lines
512 B
Systemverilog
// An example of specifying multiple bind targets with an instance list
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module foo (input logic a, input logic b, output logic c);
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// Magic happens here...
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endmodule
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module bar (input a, input b, output c);
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assign c = a ^ b;
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endmodule
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module top ();
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logic u0, v0, w0;
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logic u1, v1, w1;
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foo foo0 (.a (u0), .b (v0), .c (w0));
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foo foo1 (.a (u1), .b (v1), .c (w1));
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bind foo : foo0, foo1 bar bound_i (.*);
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always_comb begin
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assert(w0 == u0 ^ v0);
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assert(w1 == u1 ^ v1);
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end
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endmodule
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