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21 lines
372 B
Systemverilog
21 lines
372 B
Systemverilog
// A basic example of the bind construct
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module foo (input logic a, input logic b, output logic c);
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// Magic happens here...
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endmodule
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module bar (input a, input b, output c);
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assign c = a ^ b;
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endmodule
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module top ();
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logic u, v, w;
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foo foo_i (.a (u), .b (v), .c (w));
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bind foo bar bound_i (.*);
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always_comb begin
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assert(w == u ^ v);
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end
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endmodule
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