mirror of https://github.com/YosysHQ/yosys.git
20 lines
502 B
Verilog
20 lines
502 B
Verilog
//-----------------------------------------------------
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// Design Name : counter
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// File Name : counter.v
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// Function : 4 bit up counter
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// Coder : Deepak
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//-----------------------------------------------------
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module counter (clk, reset, enable, count);
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input clk, reset, enable;
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output [3:0] count;
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reg [3:0] count;
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always @ (posedge clk)
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if (reset == 1'b1) begin
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count <= 0;
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end else if ( enable == 1'b1) begin
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count <= count + 1;
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end
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endmodule
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