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18 lines
302 B
Plaintext
18 lines
302 B
Plaintext
# Block RAMs for the original Virtex.
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# The corresponding mapping file is brams_xcv_map.v
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ram block $__XILINX_BLOCKRAM_ {
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abits 12;
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widths 1 2 4 8 16 per_port;
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cost 32;
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init any;
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port srsw "A" "B" {
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clock posedge;
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clken;
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rdwr new;
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rdinit zero;
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rdsrst zero gated_clken;
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optional;
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}
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}
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