mirror of https://github.com/YosysHQ/yosys.git
225 lines
5.5 KiB
Verilog
225 lines
5.5 KiB
Verilog
module $__XILINX_BLOCKRAM_TDP_ (...);
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parameter INIT = 0;
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parameter OPTION_MODE = "FULL";
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parameter OPTION_RSTTYPE = "SYNC";
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parameter OPTION_HAS_RDFIRST = 0;
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parameter PORT_A_WIDTH = 1;
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parameter PORT_A_WR_EN_WIDTH = 1;
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parameter PORT_A_USED = 1;
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parameter PORT_A_OPTION_WRITE_MODE = "NO_CHANGE";
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parameter PORT_A_RD_INIT_VALUE = 0;
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parameter PORT_A_RD_SRST_VALUE = 0;
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parameter PORT_A_RD_ARST_VALUE = 0;
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parameter PORT_A_OPTION_RST_PRIORITY = "CE";
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parameter PORT_B_WIDTH = 1;
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parameter PORT_B_WR_EN_WIDTH = 1;
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parameter PORT_B_USED = 0;
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parameter PORT_B_OPTION_WRITE_MODE = "NO_CHANGE";
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parameter PORT_B_RD_INIT_VALUE = 0;
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parameter PORT_B_RD_SRST_VALUE = 0;
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parameter PORT_B_RD_ARST_VALUE = 0;
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parameter PORT_B_OPTION_RST_PRIORITY = "CE";
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input CLK_C;
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input PORT_A_CLK;
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input PORT_A_CLK_EN;
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input [13:0] PORT_A_ADDR;
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input [PORT_A_WIDTH-1:0] PORT_A_WR_DATA;
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input [PORT_A_WR_EN_WIDTH-1:0] PORT_A_WR_EN;
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output [PORT_A_WIDTH-1:0] PORT_A_RD_DATA;
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input PORT_A_RD_SRST;
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input PORT_A_RD_ARST;
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input PORT_B_CLK;
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input PORT_B_CLK_EN;
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input [13:0] PORT_B_ADDR;
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input [PORT_B_WIDTH-1:0] PORT_B_WR_DATA;
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input [PORT_B_WR_EN_WIDTH-1:0] PORT_B_WR_EN;
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output [PORT_B_WIDTH-1:0] PORT_B_RD_DATA;
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input PORT_B_RD_SRST;
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input PORT_B_RD_ARST;
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`include "brams_defs.vh"
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`define PARAMS_COMMON \
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.WRITE_MODE_A(PORT_A_OPTION_WRITE_MODE), \
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.WRITE_MODE_B(PORT_B_OPTION_WRITE_MODE), \
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.DATA_WIDTH_A(PORT_A_USED ? PORT_A_WIDTH : 0), \
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.DATA_WIDTH_B(PORT_B_USED ? PORT_B_WIDTH : 0), \
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.EN_RSTRAM_A("TRUE"), \
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.EN_RSTRAM_B("TRUE"), \
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.DOA_REG(0), \
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.DOB_REG(0), \
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.RST_PRIORITY_A(PORT_A_OPTION_RST_PRIORITY), \
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.RST_PRIORITY_B(PORT_B_OPTION_RST_PRIORITY), \
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.RSTTYPE(OPTION_RSTTYPE), \
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.INIT_A(ival(PORT_A_WIDTH, PORT_A_RD_INIT_VALUE)), \
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.INIT_B(ival(PORT_B_WIDTH, PORT_B_RD_INIT_VALUE)), \
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.SRVAL_A(ival(PORT_A_WIDTH, OPTION_RSTTYPE == "SYNC" ? PORT_A_RD_SRST_VALUE : PORT_A_RD_ARST_VALUE)), \
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.SRVAL_B(ival(PORT_B_WIDTH, OPTION_RSTTYPE == "SYNC" ? PORT_B_RD_SRST_VALUE : PORT_B_RD_ARST_VALUE)),
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wire RST_A = OPTION_RSTTYPE == "SYNC" ? PORT_A_RD_SRST : PORT_A_RD_ARST;
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wire RST_B = OPTION_RSTTYPE == "SYNC" ? PORT_B_RD_SRST : PORT_B_RD_ARST;
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`MAKE_DI(DI_A, DIP_A, PORT_A_WR_DATA)
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`MAKE_DI(DI_B, DIP_B, PORT_B_WR_DATA)
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`MAKE_DO(DO_A, DOP_A, PORT_A_RD_DATA)
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`MAKE_DO(DO_B, DOP_B, PORT_B_RD_DATA)
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generate
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if (OPTION_MODE == "FULL") begin
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wire [3:0] WE_A = {4{PORT_A_WR_EN}};
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wire [3:0] WE_B = {4{PORT_B_WR_EN}};
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RAMB16BWER #(
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`PARAMS_INIT_18
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`PARAMS_INITP_18
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`PARAMS_COMMON
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) _TECHMAP_REPLACE_ (
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.DOA(DO_A),
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.DOPA(DOP_A),
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.DIA(DI_A),
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.DIPA(DIP_A),
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.DOB(DO_B),
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.DOPB(DOP_B),
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.DIB(DI_B),
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.DIPB(DIP_B),
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.ADDRA(PORT_A_ADDR),
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.ADDRB(PORT_B_ADDR),
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.CLKA(PORT_A_CLK),
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.CLKB(PORT_B_CLK),
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.ENA(PORT_A_CLK_EN),
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.ENB(PORT_B_CLK_EN),
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.REGCEA(1'b0),
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.REGCEB(1'b0),
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.RSTA(RST_A),
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.RSTB(RST_B),
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.WEA(WE_A),
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.WEB(WE_B),
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);
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end else begin
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wire [1:0] WE_A = {2{PORT_A_WR_EN}};
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wire [1:0] WE_B = {2{PORT_B_WR_EN}};
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RAMB8BWER #(
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`PARAMS_INIT_9
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`PARAMS_INITP_9
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`PARAMS_COMMON
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.RAM_MODE("TDP"),
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) _TECHMAP_REPLACE_ (
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.DOADO(DO_A),
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.DOPADOP(DOP_A),
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.DIADI(DI_A),
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.DIPADIP(DIP_A),
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.DOBDO(DO_B),
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.DOPBDOP(DOP_B),
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.DIBDI(DI_B),
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.DIPBDIP(DIP_B),
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.ADDRAWRADDR(PORT_A_ADDR),
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.ADDRBRDADDR(PORT_B_ADDR),
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.CLKAWRCLK(PORT_A_CLK),
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.CLKBRDCLK(PORT_B_CLK),
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.ENAWREN(PORT_A_CLK_EN),
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.ENBRDEN(PORT_B_CLK_EN),
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.REGCEA(1'b0),
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.REGCEBREGCE(1'b0),
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.RSTA(RST_A),
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.RSTBRST(RST_B),
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.WEAWEL(WE_A),
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.WEBWEU(WE_B),
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);
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end
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endgenerate
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endmodule
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module $__XILINX_BLOCKRAM_SDP_ (...);
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parameter INIT = 0;
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parameter OPTION_RSTTYPE = "SYNC";
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parameter OPTION_WRITE_MODE = "READ_FIRST";
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parameter PORT_W_WIDTH = 1;
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parameter PORT_W_WR_EN_WIDTH = 1;
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parameter PORT_W_USED = 1;
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parameter PORT_R_WIDTH = 1;
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parameter PORT_R_USED = 0;
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parameter PORT_R_RD_INIT_VALUE = 0;
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parameter PORT_R_RD_SRST_VALUE = 0;
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parameter PORT_R_RD_ARST_VALUE = 0;
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parameter PORT_R_OPTION_RST_PRIORITY = "CE";
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input CLK_C;
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input PORT_W_CLK;
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input PORT_W_CLK_EN;
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input [13:0] PORT_W_ADDR;
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input [PORT_W_WIDTH-1:0] PORT_W_WR_DATA;
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input [PORT_W_WR_EN_WIDTH-1:0] PORT_W_WR_EN;
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input PORT_R_CLK;
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input PORT_R_CLK_EN;
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input [13:0] PORT_R_ADDR;
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output [PORT_R_WIDTH-1:0] PORT_R_RD_DATA;
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input PORT_R_RD_SRST;
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input PORT_R_RD_ARST;
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`include "brams_defs.vh"
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wire RST = OPTION_RSTTYPE == "SYNC" ? PORT_R_RD_SRST : PORT_R_RD_ARST;
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`MAKE_DI(DI, DIP, PORT_W_WR_DATA)
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`MAKE_DO(DO, DOP, PORT_R_RD_DATA)
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localparam [35:0] RST_VALUE = OPTION_RSTTYPE == "SYNC" ? PORT_R_RD_SRST_VALUE : PORT_R_RD_ARST_VALUE;
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RAMB8BWER #(
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`PARAMS_INIT_9
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`PARAMS_INITP_9
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.WRITE_MODE_A(OPTION_WRITE_MODE),
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.WRITE_MODE_B(OPTION_WRITE_MODE),
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.DATA_WIDTH_A(PORT_W_USED ? PORT_W_WIDTH : 0),
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.DATA_WIDTH_B(PORT_R_USED ? PORT_R_WIDTH : 0),
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.EN_RSTRAM_A("TRUE"),
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.EN_RSTRAM_B("TRUE"),
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.DOA_REG(0),
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.DOB_REG(0),
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.RST_PRIORITY_A("CE"),
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.RST_PRIORITY_B(PORT_R_OPTION_RST_PRIORITY),
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.RSTTYPE(OPTION_RSTTYPE),
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.INIT_A(ival(18, PORT_R_RD_INIT_VALUE[17:0])),
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.INIT_B(ival(18, PORT_R_RD_INIT_VALUE[35:18])),
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.SRVAL_A(ival(18, RST_VALUE[17:0])),
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.SRVAL_B(ival(18, RST_VALUE[35:18])),
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.RAM_MODE("SDP"),
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) _TECHMAP_REPLACE_ (
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.DOADO(DO[15:0]),
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.DOPADOP(DOP[1:0]),
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.DIADI(DI[15:0]),
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.DIPADIP(DIP[1:0]),
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.DOBDO(DO[31:16]),
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.DOPBDOP(DOP[3:2]),
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.DIBDI(DI[31:16]),
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.DIPBDIP(DIP[3:2]),
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.ADDRAWRADDR(PORT_W_ADDR),
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.ADDRBRDADDR(PORT_R_ADDR),
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.CLKAWRCLK(PORT_W_CLK),
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.CLKBRDCLK(PORT_R_CLK),
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.ENAWREN(PORT_W_CLK_EN),
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.ENBRDEN(PORT_R_CLK_EN),
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.REGCEA(1'b0),
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.REGCEBREGCE(1'b0),
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.RSTA(1'b0),
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.RSTBRST(RST),
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.WEAWEL(PORT_W_WR_EN[1:0]),
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.WEBWEU(PORT_W_WR_EN[3:2]),
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);
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endmodule
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