mirror of https://github.com/YosysHQ/yosys.git
307 lines
7.8 KiB
Verilog
307 lines
7.8 KiB
Verilog
(* abc9_box, lib_whitebox *)
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module NX_GCK_U(SI1, SI2, CMD, SO);
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input CMD;
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input SI1;
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input SI2;
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output SO;
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parameter inv_in = 1'b0;
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parameter inv_out = 1'b0;
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parameter std_mode = "BYPASS";
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wire SI1_int = inv_in ? ~SI1 : SI1;
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wire SI2_int = inv_in ? ~SI2 : SI2;
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wire SO_int;
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generate
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if (std_mode == "BYPASS") begin
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assign SO_int = SI1_int;
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end
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else if (std_mode == "MUX") begin
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assign SO_int = CMD ? SI1_int : SI2_int;
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end
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else if (std_mode == "CKS") begin
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assign SO_int = CMD ? SI1_int : 1'b0;
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end
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else if (std_mode == "CSC") begin
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assign SO_int = CMD;
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end
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else
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$error("Unrecognised std_mode");
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endgenerate
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assign SO = inv_out ? ~SO_int : SO_int;
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endmodule
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(* abc9_box, lib_whitebox *)
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module NX_RFB_U(WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, I17, I18, I19, I20
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, I21, I22, I23, I24, I25, I26, I27, I28, I29, I30, I31, I32, I33, I34, I35, I36, O1, O2, O3, O4, O5
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, O6, O7, O8, O9, O10, O11, O12, O13, O14, O15, O16, O17, O18, O19, O20, O21, O22, O23, O24, O25, O26
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, O27, O28, O29, O30, O31, O32, O33, O34, O35, O36, RA1, RA2, RA3, RA4, RA5, RA6, RA7, RA8, RA9, RA10, WA1
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, WA2, WA3, WA4, WA5, WA6, WE, WEA);
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input I1;
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input I10;
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input I11;
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input I12;
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input I13;
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input I14;
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input I15;
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input I16;
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input I17;
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input I18;
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input I19;
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input I2;
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input I20;
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input I21;
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input I22;
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input I23;
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input I24;
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input I25;
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input I26;
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input I27;
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input I28;
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input I29;
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input I3;
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input I30;
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input I31;
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input I32;
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input I33;
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input I34;
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input I35;
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input I36;
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input I4;
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input I5;
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input I6;
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input I7;
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input I8;
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input I9;
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output O1;
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output O10;
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output O11;
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output O12;
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output O13;
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output O14;
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output O15;
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output O16;
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output O17;
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output O18;
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output O19;
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output O2;
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output O20;
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output O21;
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output O22;
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output O23;
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output O24;
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output O25;
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output O26;
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output O27;
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output O28;
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output O29;
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output O3;
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output O30;
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output O31;
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output O32;
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output O33;
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output O34;
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output O35;
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output O36;
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output O4;
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output O5;
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output O6;
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output O7;
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output O8;
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output O9;
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input RA1;
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input RA10;
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input RA2;
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input RA3;
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input RA4;
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input RA5;
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input RA6;
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input RA7;
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input RA8;
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input RA9;
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input WA1;
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input WA2;
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input WA3;
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input WA4;
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input WA5;
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input WA6;
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input WCK;
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input WE;
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input WEA;
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parameter mem_ctxt = "";
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parameter mode = 0;
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parameter wck_edge = 1'b0;
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wire clock = WCK ^ wck_edge;
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localparam MEM_SIZE = mode == 2 ? 64 : 32;
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localparam MEM_WIDTH = mode == 3 ? 36 : 18;
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localparam ADDR_WIDTH = mode == 2 ? 6 : 5;
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localparam DATA_SIZE = MEM_SIZE * MEM_WIDTH;
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localparam MAX_SIZE = DATA_SIZE + MEM_SIZE + 1;
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reg [MEM_WIDTH-1:0] mem [MEM_SIZE-1:0];
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function [DATA_SIZE-1:0] convert_initval;
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input [8*MAX_SIZE-1:0] hex_initval;
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reg done;
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reg [DATA_SIZE-1:0] temp;
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reg [7:0] char;
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integer i,j;
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begin
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done = 1'b0;
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temp = 0;
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j = 0;
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for (i = 0; i < MAX_SIZE; i = i + 1) begin
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char = hex_initval[8*i +: 8];
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if (char >= "0" && char <= "1") begin
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temp[j] = char - "0";
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j = j + 1;
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end
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end
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convert_initval = temp;
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end
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endfunction
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integer i;
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reg [DATA_SIZE-1:0] mem_data;
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initial begin
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mem_data = convert_initval(mem_ctxt);
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for (i = 0; i < MEM_SIZE; i = i + 1)
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mem[i] = mem_data[MEM_WIDTH*(MEM_SIZE-i-1) +: MEM_WIDTH];
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end
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wire [ADDR_WIDTH-1:0] WA = (mode==2) ? { WA6, WA5, WA4, WA3, WA2, WA1 } : { WA5, WA4, WA3, WA2, WA1 };
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wire [36-1:0] O = { O36, O35, O34, O33, O32, O31, O30, O29, O28,
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O27, O26, O25, O24, O23, O22, O21, O20, O19,
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O18, O17, O16, O15, O14, O13, O12, O11, O10,
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O9, O8, O7, O6, O5, O4, O3, O2, O1 };
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wire [36-1:0] I = { I36, I35, I34, I33, I32, I31, I30, I29, I28,
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I27, I26, I25, I24, I23, I22, I21, I20, I19,
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I18, I17, I16, I15, I14, I13, I12, I11, I10,
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I9, I8, I7, I6, I5, I4, I3, I2, I1 };
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generate
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if (mode==0) begin
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assign O = mem[{ RA5, RA4, RA3, RA2, RA1 }];
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end
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else if (mode==1) begin
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assign O = mem[{ WA5, WA4, WA3, WA2, WA1 }];
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end
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else if (mode==2) begin
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assign O = mem[{ RA6, RA5, RA4, RA3, RA2, RA1 }];
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end
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else if (mode==3) begin
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assign O = mem[{ RA5, RA4, RA3, RA2, RA1 }];
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end
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else if (mode==4) begin
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assign O = { mem[{ RA10, RA9, RA8, RA7, RA6 }], mem[{ RA5, RA4, RA3, RA2, RA1 }] };
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end
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else
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$error("Unknown NX_RFB_U mode");
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endgenerate
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always @(posedge clock)
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if (WE)
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mem[WA] <= I[MEM_WIDTH-1:0];
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endmodule
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(* abc9_box, lib_whitebox *)
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module NX_WFG_U(R, SI, ZI, SO, ZO);
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input R;
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input SI;
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output SO;
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input ZI;
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output ZO;
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parameter delay = 0;
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parameter delay_on = 1'b0;
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parameter div_phase = 1'b0;
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parameter div_ratio = 0;
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parameter location = "";
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parameter mode = 0;
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parameter pattern = 16'b0000000000000000;
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parameter pattern_end = 0;
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parameter reset_on_cal_lock_n = 1'b0;
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parameter reset_on_pll_lock_n = 1'b0;
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parameter reset_on_pll_locka_n = 1'b0;
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parameter wfg_edge = 1'b0;
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generate
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if (mode==0) begin
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assign SO = SI;
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end
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else if (mode==1) begin
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wire clock = ZI ^ wfg_edge;
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wire reset = R || SI;
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reg [3:0] counter = 0;
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reg [15:0] rom = pattern;
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always @(posedge clock)
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begin
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if (reset)
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counter <= 4'b0;
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else
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counter <= counter + 1;
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end
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assign SO = counter == pattern_end;
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assign ZO = rom[counter];
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end
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else if (mode==2) begin
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end
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else
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$error("Unknown NX_WFG_U mode");
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endgenerate
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endmodule
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module NX_DDFR_U(CK,CKF,R,I,I2,L,O,O2);
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input CK;
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input CKF;
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input R;
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input I;
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input I2;
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input L;
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output O;
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output O2;
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parameter location = "";
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parameter path = 0;
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parameter dff_type = 1'b0;
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parameter dff_sync = 1'b0;
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parameter dff_load = 1'b0;
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wire load = dff_load ? 1'b1 : L; // reversed when compared to DFF
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wire async_reset = !dff_sync && R;
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wire sync_reset = dff_sync && R;
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generate
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if (path==1) begin
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// IDDFR
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always @(posedge CK, posedge async_reset)
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if (async_reset) O <= dff_type;
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else if (sync_reset) O <= dff_type;
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else if (load) O <= I;
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always @(posedge CKF, posedge async_reset)
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if (async_reset) O2 <= dff_type;
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else if (sync_reset) O2 <= dff_type;
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else if (load) O2 <= I;
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end
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else if (path==0 || path==2) begin
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reg q1, q2;
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// ODDFR
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always @(posedge CK, posedge async_reset)
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if (async_reset) q1 <= dff_type;
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else if (sync_reset) q1 <= dff_type;
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else if (load) q1 <= I;
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always @(posedge CKF, posedge async_reset)
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if (async_reset) q2 <= dff_type;
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else if (sync_reset) q2 <= dff_type;
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else if (load) q2 <= I2;
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assign O = CK ? q1 : q2;
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end
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else
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$error("Unknown NX_DDFR_U path");
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endgenerate
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endmodule
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