mirror of https://github.com/YosysHQ/yosys.git
702 lines
23 KiB
C++
702 lines
23 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include "libparse.h"
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#include <string.h>
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#include <errno.h>
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct cell_mapping {
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IdString cell_name;
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std::map<std::string, char> ports;
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};
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static std::map<RTLIL::IdString, cell_mapping> cell_mappings;
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static void logmap(IdString dff)
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{
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if (cell_mappings.count(dff) == 0) {
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log(" unmapped dff cell: %s\n", dff.c_str());
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} else {
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log(" %s %s (", cell_mappings[dff].cell_name.c_str(), dff.substr(1).c_str());
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bool first = true;
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for (auto &port : cell_mappings[dff].ports) {
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char arg[3] = { port.second, 0, 0 };
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if ('a' <= arg[0] && arg[0] <= 'z')
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arg[1] = arg[0] - ('a' - 'A'), arg[0] = '~';
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else
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arg[1] = arg[0], arg[0] = ' ';
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log("%s.%s(%s)", first ? "" : ", ", port.first.c_str(), arg);
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first = false;
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}
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log(");\n");
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}
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}
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static void logmap_all()
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{
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logmap(ID($_DFF_N_));
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logmap(ID($_DFF_P_));
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logmap(ID($_DFF_NN0_));
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logmap(ID($_DFF_NN1_));
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logmap(ID($_DFF_NP0_));
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logmap(ID($_DFF_NP1_));
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logmap(ID($_DFF_PN0_));
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logmap(ID($_DFF_PN1_));
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logmap(ID($_DFF_PP0_));
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logmap(ID($_DFF_PP1_));
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logmap(ID($_DFFE_NN_));
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logmap(ID($_DFFE_NP_));
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logmap(ID($_DFFE_PN_));
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logmap(ID($_DFFE_PP_));
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logmap(ID($_DFFSR_NNN_));
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logmap(ID($_DFFSR_NNP_));
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logmap(ID($_DFFSR_NPN_));
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logmap(ID($_DFFSR_NPP_));
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logmap(ID($_DFFSR_PNN_));
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logmap(ID($_DFFSR_PNP_));
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logmap(ID($_DFFSR_PPN_));
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logmap(ID($_DFFSR_PPP_));
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}
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static bool parse_next_state(const LibertyAst *cell, const LibertyAst *attr, std::string &data_name, bool &data_not_inverted, std::string &enable_name, bool &enable_not_inverted)
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{
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static pool<std::string> warned_cells{};
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if (cell == nullptr || attr == nullptr || attr->value.empty())
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return false;
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auto expr = attr->value;
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auto cell_name = cell->args[0];
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for (size_t pos = expr.find_first_of("\" \t"); pos != std::string::npos; pos = expr.find_first_of("\" \t"))
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expr.erase(pos, 1);
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// if this isn't an enable flop, the next_state variable is usually just the input pin name.
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if (expr[expr.size()-1] == '\'') {
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data_name = expr.substr(0, expr.size()-1);
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data_not_inverted = false;
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} else if (expr[0] == '!') {
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data_name = expr.substr(1, expr.size()-1);
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data_not_inverted = false;
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} else {
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data_name = expr;
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data_not_inverted = true;
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}
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for (auto child : cell->children)
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if (child->id == "pin" && child->args.size() == 1 && child->args[0] == data_name)
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return true;
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// the next_state variable isn't just a pin name; perhaps this is an enable?
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auto helper = LibertyExpression::Lexer(expr);
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auto tree = LibertyExpression::parse(helper);
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if (tree.kind == LibertyExpression::Kind::EMPTY) {
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if (!warned_cells.count(cell_name)) {
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log_warning("Invalid expression '%s' in next_state attribute of cell '%s' - skipping.\n", expr.c_str(), cell_name.c_str());
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warned_cells.insert(cell_name);
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}
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return false;
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}
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auto pin_names = pool<std::string>{};
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tree.get_pin_names(pin_names);
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// from the `ff` block, we know the flop output signal name for loopback.
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auto ff = cell->find("ff");
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if (ff == nullptr || ff->args.size() != 2)
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return false;
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auto ff_output = ff->args.at(0);
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// This test is redundant with the one in enable_pin, but we're in a
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// position that gives better diagnostics here.
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if (!pin_names.count(ff_output)) {
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if (!warned_cells.count(cell_name)) {
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log_warning("Inference failed on expression '%s' in next_state attribute of cell '%s' because it does not contain ff output '%s' - skipping.\n", expr.c_str(), cell_name.c_str(), ff_output.c_str());
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warned_cells.insert(cell_name);
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}
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return false;
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}
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data_not_inverted = true;
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data_name = "";
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enable_not_inverted = true;
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enable_name = "";
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if (pin_names.size() == 3 && pin_names.count(ff_output)) {
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pin_names.erase(ff_output);
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auto pins = std::vector<std::string>(pin_names.begin(), pin_names.end());
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int lut = 0;
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for (int n = 0; n < 8; n++) {
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auto values = dict<std::string, bool>{};
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values.insert(std::make_pair(pins[0], (n & 1) == 1));
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values.insert(std::make_pair(pins[1], (n & 2) == 2));
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values.insert(std::make_pair(ff_output, (n & 4) == 4));
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if (tree.eval(values))
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lut |= 1 << n;
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}
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// the ff output Q is in a known bit location, so we now just have to compare the LUT mask to known values to find the enable pin and polarity.
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if (lut == 0xD8) {
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data_name = pins[1];
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enable_name = pins[0];
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return true;
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}
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if (lut == 0xB8) {
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data_name = pins[0];
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enable_name = pins[1];
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return true;
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}
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enable_not_inverted = false;
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if (lut == 0xE4) {
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data_name = pins[1];
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enable_name = pins[0];
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return true;
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}
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if (lut == 0xE2) {
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data_name = pins[0];
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enable_name = pins[1];
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return true;
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}
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// this does not match an enable flop.
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}
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if (!warned_cells.count(cell_name)) {
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log_warning("Inference failed on expression '%s' in next_state attribute of cell '%s' because it does not evaluate to an enable flop - skipping.\n", expr.c_str(), cell_name.c_str());
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warned_cells.insert(cell_name);
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}
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return false;
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}
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static bool parse_pin(const LibertyAst *cell, const LibertyAst *attr, std::string &pin_name, bool &pin_pol)
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{
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if (cell == nullptr || attr == nullptr || attr->value.empty())
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return false;
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std::string value = attr->value;
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for (size_t pos = value.find_first_of("\" \t()"); pos != std::string::npos; pos = value.find_first_of("\" \t()"))
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value.erase(pos, 1);
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if (value[value.size()-1] == '\'') {
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pin_name = value.substr(0, value.size()-1);
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pin_pol = false;
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} else if (value[0] == '!') {
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pin_name = value.substr(1, value.size()-1);
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pin_pol = false;
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} else {
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pin_name = value;
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pin_pol = true;
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}
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for (auto child : cell->children)
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if (child->id == "pin" && child->args.size() == 1 && child->args[0] == pin_name)
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return true;
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/* If we end up here, the pin specified in the attribute does not exist, which is an error,
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or, the attribute contains an expression which we do not yet support.
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For now, we'll simply produce a warning to let the user know something is up.
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*/
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if (pin_name.find_first_of("^*|&") == std::string::npos) {
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log_warning("Malformed liberty file - cannot find pin '%s' in cell '%s' - skipping.\n", pin_name.c_str(), cell->args[0].c_str());
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}
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else {
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log_warning("Found unsupported expression '%s' in pin attribute of cell '%s' - skipping.\n", pin_name.c_str(), cell->args[0].c_str());
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}
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return false;
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}
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static void find_cell(const LibertyAst *ast, IdString cell_type, bool clkpol, bool has_reset, bool rstpol, bool rstval, bool has_enable, bool enapol, std::vector<std::string> &dont_use_cells)
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{
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const LibertyAst *best_cell = nullptr;
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std::map<std::string, char> best_cell_ports;
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int best_cell_pins = 0;
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bool best_cell_noninv = false;
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double best_cell_area = 0;
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if (ast->id != "library")
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log_error("Format error in liberty file.\n");
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for (auto cell : ast->children)
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{
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if (cell->id != "cell" || cell->args.size() != 1)
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continue;
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const LibertyAst *dn = cell->find("dont_use");
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if (dn != nullptr && dn->value == "true")
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continue;
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bool dont_use = false;
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for (std::string &dont_use_cell : dont_use_cells)
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{
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if (patmatch(dont_use_cell.c_str(), cell->args[0].c_str()))
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{
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dont_use = true;
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break;
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}
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}
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if (dont_use)
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continue;
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const LibertyAst *ff = cell->find("ff");
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if (ff == nullptr)
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continue;
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std::string cell_clk_pin, cell_rst_pin, cell_next_pin, cell_enable_pin;
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bool cell_clk_pol, cell_rst_pol, cell_next_pol, cell_enable_pol;
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if (!parse_pin(cell, ff->find("clocked_on"), cell_clk_pin, cell_clk_pol) || cell_clk_pol != clkpol)
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continue;
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if (!parse_next_state(cell, ff->find("next_state"), cell_next_pin, cell_next_pol, cell_enable_pin, cell_enable_pol) || (has_enable && (cell_enable_pin.empty() || cell_enable_pol != enapol)))
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continue;
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if (has_reset && rstval == false) {
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if (!parse_pin(cell, ff->find("clear"), cell_rst_pin, cell_rst_pol) || cell_rst_pol != rstpol)
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continue;
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}
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if (has_reset && rstval == true) {
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if (!parse_pin(cell, ff->find("preset"), cell_rst_pin, cell_rst_pol) || cell_rst_pol != rstpol)
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continue;
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}
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std::map<std::string, char> this_cell_ports;
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this_cell_ports[cell_clk_pin] = 'C';
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if (has_reset)
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this_cell_ports[cell_rst_pin] = 'R';
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if (has_enable)
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this_cell_ports[cell_enable_pin] = 'E';
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this_cell_ports[cell_next_pin] = 'D';
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double area = 0;
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const LibertyAst *ar = cell->find("area");
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if (ar != nullptr && !ar->value.empty())
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area = atof(ar->value.c_str());
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int num_pins = 0;
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bool found_output = false;
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bool found_noninv_output = false;
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for (auto pin : cell->children)
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{
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if (pin->id != "pin" || pin->args.size() != 1)
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continue;
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const LibertyAst *dir = pin->find("direction");
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if (dir == nullptr || dir->value == "internal")
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continue;
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num_pins++;
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if (dir->value == "input" && this_cell_ports.count(pin->args[0]) == 0)
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goto continue_cell_loop;
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const LibertyAst *func = pin->find("function");
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if (dir->value == "output" && func != nullptr) {
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std::string value = func->value;
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for (size_t pos = value.find_first_of("\" \t"); pos != std::string::npos; pos = value.find_first_of("\" \t"))
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value.erase(pos, 1);
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if (value == ff->args[0]) {
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this_cell_ports[pin->args[0]] = cell_next_pol ? 'Q' : 'q';
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if (cell_next_pol)
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found_noninv_output = true;
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found_output = true;
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} else
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if (value == ff->args[1]) {
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this_cell_ports[pin->args[0]] = cell_next_pol ? 'q' : 'Q';
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if (!cell_next_pol)
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found_noninv_output = true;
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found_output = true;
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}
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}
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if (this_cell_ports.count(pin->args[0]) == 0)
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this_cell_ports[pin->args[0]] = 0;
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}
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if (!found_output || (best_cell != nullptr && (num_pins > best_cell_pins || (best_cell_noninv && !found_noninv_output))))
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continue;
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if (best_cell != nullptr && num_pins == best_cell_pins && area > best_cell_area)
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continue;
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best_cell = cell;
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best_cell_pins = num_pins;
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best_cell_area = area;
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best_cell_noninv = found_noninv_output;
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best_cell_ports.swap(this_cell_ports);
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continue_cell_loop:;
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}
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if (best_cell != nullptr) {
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log(" cell %s (%sinv, pins=%d, area=%.2f) is a direct match for cell type %s.\n",
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best_cell->args[0].c_str(), best_cell_noninv ? "non" : "", best_cell_pins, best_cell_area, cell_type.c_str());
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cell_mappings[cell_type].cell_name = RTLIL::escape_id(best_cell->args[0]);
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cell_mappings[cell_type].ports = best_cell_ports;
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}
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}
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static void find_cell_sr(const LibertyAst *ast, IdString cell_type, bool clkpol, bool setpol, bool clrpol, bool has_enable, bool enapol, std::vector<std::string> &dont_use_cells)
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{
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const LibertyAst *best_cell = nullptr;
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std::map<std::string, char> best_cell_ports;
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int best_cell_pins = 0;
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bool best_cell_noninv = false;
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double best_cell_area = 0;
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log_assert(!enapol && "set/reset cell with enable is unimplemented due to lack of cells for testing");
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if (ast->id != "library")
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log_error("Format error in liberty file.\n");
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for (auto cell : ast->children)
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{
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if (cell->id != "cell" || cell->args.size() != 1)
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continue;
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const LibertyAst *dn = cell->find("dont_use");
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if (dn != nullptr && dn->value == "true")
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continue;
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bool dont_use = false;
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for (std::string &dont_use_cell : dont_use_cells)
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{
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if (patmatch(dont_use_cell.c_str(), cell->args[0].c_str()))
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{
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dont_use = true;
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break;
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}
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}
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if (dont_use)
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continue;
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const LibertyAst *ff = cell->find("ff");
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if (ff == nullptr)
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continue;
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std::string cell_clk_pin, cell_set_pin, cell_clr_pin, cell_next_pin, cell_enable_pin;
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bool cell_clk_pol, cell_set_pol, cell_clr_pol, cell_next_pol, cell_enable_pol;
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if (!parse_pin(cell, ff->find("clocked_on"), cell_clk_pin, cell_clk_pol) || cell_clk_pol != clkpol)
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continue;
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if (!parse_next_state(cell, ff->find("next_state"), cell_next_pin, cell_next_pol, cell_enable_pin, cell_enable_pol))
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continue;
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if (!parse_pin(cell, ff->find("preset"), cell_set_pin, cell_set_pol) || cell_set_pol != setpol)
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continue;
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if (!parse_pin(cell, ff->find("clear"), cell_clr_pin, cell_clr_pol) || cell_clr_pol != clrpol)
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continue;
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std::map<std::string, char> this_cell_ports;
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this_cell_ports[cell_clk_pin] = 'C';
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this_cell_ports[cell_set_pin] = 'S';
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this_cell_ports[cell_clr_pin] = 'R';
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if (has_enable)
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this_cell_ports[cell_enable_pin] = 'E';
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this_cell_ports[cell_next_pin] = 'D';
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double area = 0;
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const LibertyAst *ar = cell->find("area");
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if (ar != nullptr && !ar->value.empty())
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area = atof(ar->value.c_str());
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int num_pins = 0;
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bool found_output = false;
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bool found_noninv_output = false;
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for (auto pin : cell->children)
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{
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if (pin->id != "pin" || pin->args.size() != 1)
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continue;
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const LibertyAst *dir = pin->find("direction");
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if (dir == nullptr || dir->value == "internal")
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continue;
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num_pins++;
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if (dir->value == "input" && this_cell_ports.count(pin->args[0]) == 0)
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goto continue_cell_loop;
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const LibertyAst *func = pin->find("function");
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if (dir->value == "output" && func != nullptr) {
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std::string value = func->value;
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for (size_t pos = value.find_first_of("\" \t"); pos != std::string::npos; pos = value.find_first_of("\" \t"))
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value.erase(pos, 1);
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if (value == ff->args[0]) {
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this_cell_ports[pin->args[0]] = cell_next_pol ? 'Q' : 'q';
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if (cell_next_pol)
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found_noninv_output = true;
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found_output = true;
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} else
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if (value == ff->args[1]) {
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this_cell_ports[pin->args[0]] = cell_next_pol ? 'q' : 'Q';
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if (!cell_next_pol)
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found_noninv_output = true;
|
|
found_output = true;
|
|
}
|
|
}
|
|
|
|
if (this_cell_ports.count(pin->args[0]) == 0)
|
|
this_cell_ports[pin->args[0]] = 0;
|
|
}
|
|
|
|
if (!found_output || (best_cell != nullptr && (num_pins > best_cell_pins || (best_cell_noninv && !found_noninv_output))))
|
|
continue;
|
|
|
|
if (best_cell != nullptr && num_pins == best_cell_pins && area > best_cell_area)
|
|
continue;
|
|
|
|
best_cell = cell;
|
|
best_cell_pins = num_pins;
|
|
best_cell_area = area;
|
|
best_cell_noninv = found_noninv_output;
|
|
best_cell_ports.swap(this_cell_ports);
|
|
continue_cell_loop:;
|
|
}
|
|
|
|
if (best_cell != nullptr) {
|
|
log(" cell %s (%sinv, pins=%d, area=%.2f) is a direct match for cell type %s.\n",
|
|
best_cell->args[0].c_str(), best_cell_noninv ? "non" : "", best_cell_pins, best_cell_area, cell_type.c_str());
|
|
cell_mappings[cell_type].cell_name = RTLIL::escape_id(best_cell->args[0]);
|
|
cell_mappings[cell_type].ports = best_cell_ports;
|
|
}
|
|
}
|
|
|
|
static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module)
|
|
{
|
|
log("Mapping DFF cells in module `%s':\n", module->name.c_str());
|
|
|
|
dict<SigBit, pool<Cell*>> notmap;
|
|
SigMap sigmap(module);
|
|
|
|
std::vector<RTLIL::Cell*> cell_list;
|
|
for (auto cell : module->cells()) {
|
|
if (design->selected(module, cell) && cell_mappings.count(cell->type) > 0)
|
|
cell_list.push_back(cell);
|
|
if (cell->type == ID($_NOT_))
|
|
notmap[sigmap(cell->getPort(ID::A))].insert(cell);
|
|
}
|
|
|
|
std::map<std::string, int> stats;
|
|
for (auto cell : cell_list)
|
|
{
|
|
auto cell_type = cell->type;
|
|
auto cell_name = cell->name;
|
|
auto cell_connections = cell->connections();
|
|
std::string src = cell->get_src_attribute();
|
|
|
|
module->remove(cell);
|
|
|
|
cell_mapping &cm = cell_mappings[cell_type];
|
|
RTLIL::Cell *new_cell = module->addCell(cell_name, cm.cell_name);
|
|
|
|
new_cell->set_src_attribute(src);
|
|
|
|
bool has_q = false, has_qn = false;
|
|
for (auto &port : cm.ports) {
|
|
if (port.second == 'Q') has_q = true;
|
|
if (port.second == 'q') has_qn = true;
|
|
}
|
|
|
|
for (auto &port : cm.ports) {
|
|
RTLIL::SigSpec sig;
|
|
if ('A' <= port.second && port.second <= 'Z') {
|
|
sig = cell_connections[std::string("\\") + port.second];
|
|
} else
|
|
if (port.second == 'q') {
|
|
RTLIL::SigSpec old_sig = cell_connections[std::string("\\") + char(port.second - ('a' - 'A'))];
|
|
sig = module->addWire(NEW_ID, GetSize(old_sig));
|
|
if (has_q && has_qn) {
|
|
for (auto &it : notmap[sigmap(old_sig)]) {
|
|
module->connect(it->getPort(ID::Y), sig);
|
|
it->setPort(ID::Y, module->addWire(NEW_ID, GetSize(old_sig)));
|
|
}
|
|
} else {
|
|
module->addNotGate(NEW_ID, sig, old_sig);
|
|
}
|
|
} else
|
|
if ('a' <= port.second && port.second <= 'z') {
|
|
sig = cell_connections[std::string("\\") + char(port.second - ('a' - 'A'))];
|
|
sig = module->NotGate(NEW_ID, sig);
|
|
} else
|
|
if (port.second == '0' || port.second == '1') {
|
|
sig = RTLIL::SigSpec(port.second == '0' ? 0 : 1, 1);
|
|
} else
|
|
if (port.second == 0) {
|
|
sig = module->addWire(NEW_ID);
|
|
} else
|
|
log_abort();
|
|
new_cell->setPort("\\" + port.first, sig);
|
|
}
|
|
|
|
stats[stringf(" mapped %%d %s cells to %s cells.\n", cell_type.c_str(), new_cell->type.c_str())]++;
|
|
}
|
|
|
|
for (auto &stat: stats)
|
|
log(stat.first.c_str(), stat.second);
|
|
}
|
|
|
|
struct DfflibmapPass : public Pass {
|
|
DfflibmapPass() : Pass("dfflibmap", "technology mapping of flip-flops") { }
|
|
void help() override
|
|
{
|
|
log("\n");
|
|
log(" dfflibmap [-prepare] [-map-only] [-info] [-dont_use <cell_name>] -liberty <file> [selection]\n");
|
|
log("\n");
|
|
log("Map internal flip-flop cells to the flip-flop cells in the technology\n");
|
|
log("library specified in the given liberty file.\n");
|
|
log("\n");
|
|
log("This pass may add inverters as needed. Therefore it is recommended to\n");
|
|
log("first run this pass and then map the logic paths to the target technology.\n");
|
|
log("\n");
|
|
log("When called with -prepare, this command will convert the internal FF cells\n");
|
|
log("to the internal cell types that best match the cells found in the given\n");
|
|
log("liberty file, but won't actually map them to the target cells.\n");
|
|
log("\n");
|
|
log("When called with -map-only, this command will only map internal cell\n");
|
|
log("types that are already of exactly the right type to match the target\n");
|
|
log("cells, leaving remaining internal cells untouched.\n");
|
|
log("\n");
|
|
log("When called with -info, this command will only print the target cell\n");
|
|
log("list, along with their associated internal cell types, and the arguments\n");
|
|
log("that would be passed to the dfflegalize pass. The design will not be\n");
|
|
log("changed.\n");
|
|
log("\n");
|
|
log("When called with -dont_use, this command will not map to the specified cell\n");
|
|
log("name as an alternative to setting the dont_use property in the Liberty file.\n");
|
|
log("This argument can be called multiple times with different cell names. This\n");
|
|
log("argument also supports simple glob patterns in the cell name.\n");
|
|
log("\n");
|
|
}
|
|
void execute(std::vector<std::string> args, RTLIL::Design *design) override
|
|
{
|
|
log_header(design, "Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).\n");
|
|
log_push();
|
|
|
|
std::string liberty_file;
|
|
bool prepare_mode = false;
|
|
bool map_only_mode = false;
|
|
bool info_mode = false;
|
|
|
|
std::vector<std::string> dont_use_cells;
|
|
|
|
size_t argidx;
|
|
for (argidx = 1; argidx < args.size(); argidx++)
|
|
{
|
|
std::string arg = args[argidx];
|
|
if (arg == "-liberty" && argidx+1 < args.size()) {
|
|
liberty_file = args[++argidx];
|
|
rewrite_filename(liberty_file);
|
|
continue;
|
|
}
|
|
if (arg == "-prepare") {
|
|
prepare_mode = true;
|
|
continue;
|
|
}
|
|
if (arg == "-map-only") {
|
|
map_only_mode = true;
|
|
continue;
|
|
}
|
|
if (arg == "-info") {
|
|
info_mode = true;
|
|
continue;
|
|
}
|
|
if (arg == "-dont_use" && argidx+1 < args.size()) {
|
|
dont_use_cells.push_back(args[++argidx]);
|
|
continue;
|
|
}
|
|
break;
|
|
}
|
|
extra_args(args, argidx, design);
|
|
|
|
int modes = 0;
|
|
if (prepare_mode)
|
|
modes++;
|
|
if (map_only_mode)
|
|
modes++;
|
|
if (info_mode)
|
|
modes++;
|
|
if (modes > 1)
|
|
log_cmd_error("Only one of -prepare, -map-only, or -info options should be given!\n");
|
|
|
|
if (liberty_file.empty())
|
|
log_cmd_error("Missing `-liberty liberty_file' option!\n");
|
|
|
|
std::ifstream f;
|
|
f.open(liberty_file.c_str());
|
|
if (f.fail())
|
|
log_cmd_error("Can't open liberty file `%s': %s\n", liberty_file.c_str(), strerror(errno));
|
|
LibertyParser libparser(f);
|
|
f.close();
|
|
|
|
find_cell(libparser.ast, ID($_DFF_N_), false, false, false, false, false, false, dont_use_cells);
|
|
find_cell(libparser.ast, ID($_DFF_P_), true, false, false, false, false, false, dont_use_cells);
|
|
|
|
find_cell(libparser.ast, ID($_DFF_NN0_), false, true, false, false, false, false, dont_use_cells);
|
|
find_cell(libparser.ast, ID($_DFF_NN1_), false, true, false, true, false, false, dont_use_cells);
|
|
find_cell(libparser.ast, ID($_DFF_NP0_), false, true, true, false, false, false, dont_use_cells);
|
|
find_cell(libparser.ast, ID($_DFF_NP1_), false, true, true, true, false, false, dont_use_cells);
|
|
find_cell(libparser.ast, ID($_DFF_PN0_), true, true, false, false, false, false, dont_use_cells);
|
|
find_cell(libparser.ast, ID($_DFF_PN1_), true, true, false, true, false, false, dont_use_cells);
|
|
find_cell(libparser.ast, ID($_DFF_PP0_), true, true, true, false, false, false, dont_use_cells);
|
|
find_cell(libparser.ast, ID($_DFF_PP1_), true, true, true, true, false, false, dont_use_cells);
|
|
|
|
find_cell(libparser.ast, ID($_DFFE_NN_), false, false, false, false, true, false, dont_use_cells);
|
|
find_cell(libparser.ast, ID($_DFFE_NP_), false, false, false, false, true, true, dont_use_cells);
|
|
find_cell(libparser.ast, ID($_DFFE_PN_), true, false, false, false, true, false, dont_use_cells);
|
|
find_cell(libparser.ast, ID($_DFFE_PP_), true, false, false, false, true, true, dont_use_cells);
|
|
|
|
find_cell_sr(libparser.ast, ID($_DFFSR_NNN_), false, false, false, false, false, dont_use_cells);
|
|
find_cell_sr(libparser.ast, ID($_DFFSR_NNP_), false, false, true, false, false, dont_use_cells);
|
|
find_cell_sr(libparser.ast, ID($_DFFSR_NPN_), false, true, false, false, false, dont_use_cells);
|
|
find_cell_sr(libparser.ast, ID($_DFFSR_NPP_), false, true, true, false, false, dont_use_cells);
|
|
find_cell_sr(libparser.ast, ID($_DFFSR_PNN_), true, false, false, false, false, dont_use_cells);
|
|
find_cell_sr(libparser.ast, ID($_DFFSR_PNP_), true, false, true, false, false, dont_use_cells);
|
|
find_cell_sr(libparser.ast, ID($_DFFSR_PPN_), true, true, false, false, false, dont_use_cells);
|
|
find_cell_sr(libparser.ast, ID($_DFFSR_PPP_), true, true, true, false, false, dont_use_cells);
|
|
|
|
log(" final dff cell mappings:\n");
|
|
logmap_all();
|
|
|
|
if (!map_only_mode) {
|
|
std::string dfflegalize_cmd = "dfflegalize";
|
|
for (auto it : cell_mappings)
|
|
dfflegalize_cmd += stringf(" -cell %s 01", it.first.c_str());
|
|
dfflegalize_cmd += " t:$_DFF* t:$_SDFF*";
|
|
if (info_mode) {
|
|
log("dfflegalize command line: %s\n", dfflegalize_cmd.c_str());
|
|
} else {
|
|
Pass::call(design, dfflegalize_cmd);
|
|
}
|
|
}
|
|
|
|
if (!prepare_mode && !info_mode) {
|
|
for (auto module : design->selected_modules())
|
|
if (!module->get_blackbox_attribute())
|
|
dfflibmap(design, module);
|
|
}
|
|
|
|
log_pop();
|
|
cell_mappings.clear();
|
|
}
|
|
} DfflibmapPass;
|
|
|
|
PRIVATE_NAMESPACE_END
|