mirror of https://github.com/YosysHQ/yosys.git
141 lines
3.9 KiB
C++
141 lines
3.9 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct DeminoutPass : public Pass {
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DeminoutPass() : Pass("deminout", "demote inout ports to input or output") { }
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void help() override
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{
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log("\n");
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log(" deminout [options] [selection]\n");
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log("\n");
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log("\"Demote\" inout ports to input or output ports, if possible.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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log_header(design, "Executing DEMINOUT pass (demote inout ports to input or output).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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// if (args[argidx] == "-bits") {
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// flag_bits = true;
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// continue;
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// }
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break;
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}
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extra_args(args, argidx, design);
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bool keep_running = true;
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while (keep_running)
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{
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keep_running = false;
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for (auto module : design->selected_modules())
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{
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SigMap sigmap(module);
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pool<SigBit> bits_written, bits_used, bits_inout, bits_tribuf;
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dict<SigBit, int> bits_numports;
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for (auto wire : module->wires())
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if (wire->port_id)
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for (auto bit : sigmap(wire))
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bits_numports[bit]++;
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for (auto cell : module->cells())
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for (auto &conn : cell->connections())
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{
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bool cellport_out = cell->output(conn.first) || !cell->known();
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bool cellport_in = cell->input(conn.first) || !cell->known();
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if (cellport_out && cellport_in)
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for (auto bit : sigmap(conn.second))
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bits_inout.insert(bit);
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if (cellport_out)
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for (auto bit : sigmap(conn.second))
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bits_written.insert(bit);
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if (cellport_in)
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for (auto bit : sigmap(conn.second))
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bits_used.insert(bit);
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if (conn.first == ID::Y && cell->type.in(ID($mux), ID($pmux), ID($_MUX_), ID($_TBUF_), ID($tribuf)))
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{
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bool tribuf = cell->type.in(ID($_TBUF_), ID($tribuf));
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if (!tribuf) {
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for (auto &c : cell->connections()) {
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if (!c.first.in(ID::A, ID::B))
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continue;
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for (auto b : sigmap(c.second))
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if (b == State::Sz)
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tribuf = true;
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}
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}
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if (tribuf)
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for (auto bit : sigmap(conn.second))
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bits_tribuf.insert(bit);
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}
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}
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for (auto wire : module->selected_wires())
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if (wire->port_input && wire->port_output)
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{
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bool new_input = false;
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bool new_output = false;
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for (auto bit : sigmap(wire))
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{
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if (bits_numports[bit] > 1 || bits_inout.count(bit))
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new_input = true, new_output = true;
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if (!bit.wire)
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new_output = true;
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if (bits_written.count(bit)) {
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new_output = true;
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if (bits_tribuf.count(bit))
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goto tribuf_bit;
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} else {
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tribuf_bit:
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new_input = true;
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}
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}
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if (new_input != new_output) {
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log("Demoting inout port %s.%s to %s.\n", log_id(module), log_id(wire), new_input ? "input" : "output");
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wire->port_input = new_input;
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wire->port_output = new_output;
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keep_running = true;
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}
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}
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}
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}
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}
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} DeminoutPass;
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PRIVATE_NAMESPACE_END
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