mirror of https://github.com/YosysHQ/yosys.git
353 lines
13 KiB
C++
353 lines
13 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include "kernel/ffinit.h"
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#include "kernel/ff.h"
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#include "kernel/mem.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct SampledSig {
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SigSpec sampled, current;
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SigSpec &operator[](bool get_current) { return get_current ? current : sampled; }
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};
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struct Clk2fflogicPass : public Pass {
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Clk2fflogicPass() : Pass("clk2fflogic", "convert clocked FFs to generic $ff cells") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" clk2fflogic [options] [selection]\n");
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log("\n");
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log("This command replaces clocked flip-flops with generic $ff cells that use the\n");
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log("implicit global clock. This is useful for formal verification of designs with\n");
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log("multiple clocks.\n");
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log("\n");
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log("This pass assumes negative hold time for the async FF inputs. For example when\n");
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log("a reset deasserts with the clock edge, then the FF output will still drive the\n");
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log("reset value in the next cycle regardless of the data-in value at the time of\n");
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log("the clock edge.\n");
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log("\n");
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log(" -nolower\n");
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log(" Do not automatically run 'chformal -lower' to lower $check cells.\n");
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log("\n");
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log(" -nopeepopt\n");
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log(" Do not automatically run 'peepopt -formalclk' to rewrite clock patterns\n");
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log(" to more formal friendly forms.\n");
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log("\n");
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}
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// Active-high sampled and current value of a level-triggered control signal. Initial sampled values is low/non-asserted.
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SampledSig sample_control(Module *module, SigSpec sig, bool polarity, bool is_fine) {
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if (!polarity) {
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if (is_fine)
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sig = module->NotGate(NEW_ID, sig);
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else
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sig = module->Not(NEW_ID, sig);
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}
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std::string sig_str = log_signal(sig);
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sig_str.erase(std::remove(sig_str.begin(), sig_str.end(), ' '), sig_str.end());
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Wire *sampled_sig = module->addWire(NEW_ID_SUFFIX(stringf("%s#sampled", sig_str.c_str())), GetSize(sig));
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sampled_sig->attributes[ID::init] = RTLIL::Const(State::S0, GetSize(sig));
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if (is_fine)
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module->addFfGate(NEW_ID, sig, sampled_sig);
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else
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module->addFf(NEW_ID, sig, sampled_sig);
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return {sampled_sig, sig};
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}
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// Active-high trigger signal for an edge-triggered control signal. Initial values is low/non-edge.
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SigSpec sample_control_edge(Module *module, SigSpec sig, bool polarity, bool is_fine) {
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std::string sig_str = log_signal(sig);
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sig_str.erase(std::remove(sig_str.begin(), sig_str.end(), ' '), sig_str.end());
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Wire *sampled_sig = module->addWire(NEW_ID_SUFFIX(stringf("%s#sampled", sig_str.c_str())), GetSize(sig));
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sampled_sig->attributes[ID::init] = RTLIL::Const(polarity ? State::S1 : State::S0, GetSize(sig));
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if (is_fine)
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module->addFfGate(NEW_ID, sig, sampled_sig);
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else
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module->addFf(NEW_ID, sig, sampled_sig);
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return module->Eqx(NEW_ID, {sampled_sig, sig}, polarity ? SigSpec {State::S0, State::S1} : SigSpec {State::S1, State::S0});
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}
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// Sampled and current value of a data signal.
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SampledSig sample_data(Module *module, SigSpec sig, RTLIL::Const init, bool is_fine, bool set_attribute = false) {
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std::string sig_str = log_signal(sig);
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sig_str.erase(std::remove(sig_str.begin(), sig_str.end(), ' '), sig_str.end());
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Wire *sampled_sig = module->addWire(NEW_ID_SUFFIX(stringf("%s#sampled", sig_str.c_str())), GetSize(sig));
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sampled_sig->attributes[ID::init] = init;
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Cell *cell;
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if (is_fine)
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cell = module->addFfGate(NEW_ID, sig, sampled_sig);
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else
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cell = module->addFf(NEW_ID, sig, sampled_sig);
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if (set_attribute) {
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for (auto &chunk : sig.chunks())
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if (chunk.wire != nullptr)
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chunk.wire->set_bool_attribute(ID::keep);
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cell->set_bool_attribute(ID(clk2fflogic));
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}
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return {sampled_sig, sig};
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}
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SigSpec mux(Module *module, SigSpec a, SigSpec b, SigSpec s, bool is_fine) {
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if (is_fine)
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return module->MuxGate(NEW_ID, a, b, s);
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else
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return module->Mux(NEW_ID, a, b, s);
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}
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SigSpec bitwise_sr(Module *module, SigSpec a, SigSpec s, SigSpec r, bool is_fine) {
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if (is_fine)
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return module->AndGate(NEW_ID, module->OrGate(NEW_ID, a, s), module->NotGate(NEW_ID, r));
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else
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return module->And(NEW_ID, module->Or(NEW_ID, a, s), module->Not(NEW_ID, r));
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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bool flag_nolower = false;
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bool flag_nopeepopt = false;
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log_header(design, "Executing CLK2FFLOGIC pass (convert clocked FFs to generic $ff cells).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-nolower") {
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flag_nolower = true;
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continue;
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}
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if (args[argidx] == "-nopeepopt") {
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flag_nopeepopt = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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if (!flag_nopeepopt) {
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log_push();
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Pass::call(design, "peepopt -formalclk");
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log_pop();
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}
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bool have_check_cells = false;
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for (auto module : design->selected_modules())
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{
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SigMap sigmap(module);
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FfInitVals initvals(&sigmap, module);
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for (auto &mem : Mem::get_selected_memories(module))
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{
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for (int i = 0; i < GetSize(mem.rd_ports); i++) {
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auto &port = mem.rd_ports[i];
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if (port.clk_enable)
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log_error("Read port %d of memory %s.%s is clocked. This is not supported by \"clk2fflogic\"! "
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"Call \"memory\" with -nordff to avoid this error.\n", i, log_id(mem.memid), log_id(module));
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}
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for (int i = 0; i < GetSize(mem.wr_ports); i++)
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{
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auto &port = mem.wr_ports[i];
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if (!port.clk_enable)
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continue;
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log("Modifying write port %d on memory %s.%s: CLK=%s, A=%s, D=%s\n",
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i, log_id(module), log_id(mem.memid), log_signal(port.clk),
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log_signal(port.addr), log_signal(port.data));
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Wire *past_clk = module->addWire(NEW_ID_SUFFIX(stringf("%s#%d#past_clk#%s", log_id(mem.memid), i, log_signal(port.clk))));
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past_clk->attributes[ID::init] = port.clk_polarity ? State::S1 : State::S0;
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module->addFf(NEW_ID, port.clk, past_clk);
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SigSpec clock_edge_pattern;
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if (port.clk_polarity) {
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clock_edge_pattern.append(State::S0);
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clock_edge_pattern.append(State::S1);
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} else {
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clock_edge_pattern.append(State::S1);
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clock_edge_pattern.append(State::S0);
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}
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SigSpec clock_edge = module->Eqx(NEW_ID, {port.clk, SigSpec(past_clk)}, clock_edge_pattern);
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SigSpec en_q = module->addWire(NEW_ID_SUFFIX(stringf("%s#%d#en_q", log_id(mem.memid), i)), GetSize(port.en));
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module->addFf(NEW_ID, port.en, en_q);
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SigSpec addr_q = module->addWire(NEW_ID_SUFFIX(stringf("%s#%d#addr_q", log_id(mem.memid), i)), GetSize(port.addr));
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module->addFf(NEW_ID, port.addr, addr_q);
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SigSpec data_q = module->addWire(NEW_ID_SUFFIX(stringf("%s#%d#data_q", log_id(mem.memid), i)), GetSize(port.data));
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module->addFf(NEW_ID, port.data, data_q);
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port.clk = State::S0;
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port.en = module->Mux(NEW_ID, Const(0, GetSize(en_q)), en_q, clock_edge);
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port.addr = addr_q;
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port.data = data_q;
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port.clk_enable = false;
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port.clk_polarity = false;
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}
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mem.emit();
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}
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SigBit initstate;
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for (auto cell : vector<Cell*>(module->selected_cells()))
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{
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if (cell->type.in(ID($print), ID($check)))
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{
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if (cell->type == ID($check))
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have_check_cells = true;
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bool trg_enable = cell->getParam(ID(TRG_ENABLE)).as_bool();
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if (!trg_enable)
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continue;
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int trg_width = cell->getParam(ID(TRG_WIDTH)).as_int();
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if (trg_width == 0) {
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if (initstate == State::S0)
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initstate = module->Initstate(NEW_ID);
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SigBit sig_en = cell->getPort(ID::EN);
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cell->setPort(ID::EN, module->And(NEW_ID, sig_en, initstate));
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} else {
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SigBit sig_en = cell->getPort(ID::EN);
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SigSpec sig_args = cell->getPort(ID::ARGS);
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Const trg_polarity = cell->getParam(ID(TRG_POLARITY));
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SigSpec sig_trg = cell->getPort(ID::TRG);
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SigSpec sig_trg_sampled;
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for (auto const &bit : sig_trg)
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sig_trg_sampled.append(sample_control_edge(module, bit, trg_polarity[GetSize(sig_trg_sampled)] == State::S1, false));
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SigSpec sig_args_sampled = sample_data(module, sig_args, Const(State::S0, GetSize(sig_args)), false, false).sampled;
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SigBit sig_en_sampled = sample_data(module, sig_en, State::S0, false, false).sampled;
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SigBit sig_trg_combined = module->ReduceOr(NEW_ID, sig_trg_sampled);
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cell->setPort(ID::EN, module->And(NEW_ID, sig_en_sampled, sig_trg_combined));
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cell->setPort(ID::ARGS, sig_args_sampled);
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if (cell->type == ID($check)) {
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SigBit sig_a = cell->getPort(ID::A);
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SigBit sig_a_sampled = sample_data(module, sig_a, State::S1, false, false).sampled;
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cell->setPort(ID::A, sig_a_sampled);
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}
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}
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cell->setPort(ID::TRG, SigSpec());
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cell->setParam(ID::TRG_ENABLE, false);
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cell->setParam(ID::TRG_WIDTH, 0);
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cell->setParam(ID::TRG_POLARITY, false);
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cell->set_bool_attribute(ID(trg_on_gclk));
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continue;
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}
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if (!RTLIL::builtin_ff_cell_types().count(cell->type))
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continue;
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FfData ff(&initvals, cell);
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if (ff.has_gclk) {
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// Already a $ff or $_FF_ cell.
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continue;
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}
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if (ff.has_clk) {
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log("Replacing %s.%s (%s): CLK=%s, D=%s, Q=%s\n",
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log_id(module), log_id(cell), log_id(cell->type),
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log_signal(ff.sig_clk), log_signal(ff.sig_d), log_signal(ff.sig_q));
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} else if (ff.has_aload) {
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log("Replacing %s.%s (%s): EN=%s, D=%s, Q=%s\n",
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log_id(module), log_id(cell), log_id(cell->type),
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log_signal(ff.sig_aload), log_signal(ff.sig_ad), log_signal(ff.sig_q));
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} else {
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// $sr.
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log("Replacing %s.%s (%s): SET=%s, CLR=%s, Q=%s\n",
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log_id(module), log_id(cell), log_id(cell->type),
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log_signal(ff.sig_set), log_signal(ff.sig_clr), log_signal(ff.sig_q));
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}
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ff.remove();
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if (ff.has_clk)
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ff.unmap_ce_srst();
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auto next_q = sample_data(module, ff.sig_q, ff.val_init, ff.is_fine, true).sampled;
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if (ff.has_clk) {
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// The init value for the sampled d is never used, so we can set it to fixed zero, reducing uninit'd FFs
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auto sampled_d = sample_data(module, ff.sig_d, RTLIL::Const(State::S0, ff.width), ff.is_fine);
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auto clk_edge = sample_control_edge(module, ff.sig_clk, ff.pol_clk, ff.is_fine);
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next_q = mux(module, next_q, sampled_d.sampled, clk_edge, ff.is_fine);
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}
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SampledSig sampled_aload, sampled_ad, sampled_set, sampled_clr, sampled_arst;
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// The check for a constant sig_aload is also done by opt_dff, but when using verific and running
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// clk2fflogic before opt_dff (which does more and possibly unwanted optimizations) this check avoids
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// generating a lot of extra logic.
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bool has_nonconst_aload = ff.has_aload && ff.sig_aload != (ff.pol_aload ? State::S0 : State::S1);
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if (has_nonconst_aload) {
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sampled_aload = sample_control(module, ff.sig_aload, ff.pol_aload, ff.is_fine);
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// The init value for the sampled ad is never used, so we can set it to fixed zero, reducing uninit'd FFs
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sampled_ad = sample_data(module, ff.sig_ad, RTLIL::Const(State::S0, ff.width), ff.is_fine);
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}
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if (ff.has_sr) {
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sampled_set = sample_control(module, ff.sig_set, ff.pol_set, ff.is_fine);
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sampled_clr = sample_control(module, ff.sig_clr, ff.pol_clr, ff.is_fine);
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}
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if (ff.has_arst)
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sampled_arst = sample_control(module, ff.sig_arst, ff.pol_arst, ff.is_fine);
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// First perform updates using _only_ sampled values, then again using _only_ current values. Unlike the previous
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// implementation, this approach correctly handles all the cases of multiple signals changing simultaneously.
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for (int current = 0; current < 2; current++) {
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if (has_nonconst_aload)
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next_q = mux(module, next_q, sampled_ad[current], sampled_aload[current], ff.is_fine);
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if (ff.has_sr)
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next_q = bitwise_sr(module, next_q, sampled_set[current], sampled_clr[current], ff.is_fine);
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if (ff.has_arst)
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next_q = mux(module, next_q, ff.val_arst, sampled_arst[current], ff.is_fine);
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}
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module->connect(ff.sig_q, next_q);
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}
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}
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if (have_check_cells && !flag_nolower) {
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log_push();
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Pass::call(design, "chformal -lower");
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log_pop();
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}
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}
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} Clk2fflogicPass;
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PRIVATE_NAMESPACE_END
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