mirror of https://github.com/YosysHQ/yosys.git
82 lines
2.9 KiB
C++
82 lines
2.9 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/mem.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct MemoryMemxPass : public Pass {
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MemoryMemxPass() : Pass("memory_memx", "emulate vlog sim behavior for mem ports") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" memory_memx [selection]\n");
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log("\n");
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log("This pass adds additional circuitry that emulates the Verilog simulation\n");
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log("behavior for out-of-bounds memory reads and writes.\n");
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log("\n");
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}
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SigSpec make_addr_check(Mem &mem, SigSpec addr) {
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int start_addr = mem.start_offset;
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int end_addr = mem.start_offset + mem.size;
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addr.extend_u0(32);
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SigSpec res = mem.module->Nex(NEW_ID, mem.module->ReduceXor(NEW_ID, addr), mem.module->ReduceXor(NEW_ID, {addr, State::S1}));
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if (start_addr != 0)
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res = mem.module->LogicAnd(NEW_ID, res, mem.module->Ge(NEW_ID, addr, start_addr));
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res = mem.module->LogicAnd(NEW_ID, res, mem.module->Lt(NEW_ID, addr, end_addr));
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return res;
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override {
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log_header(design, "Executing MEMORY_MEMX pass (emit soft logic for out-of-bounds handling).\n");
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extra_args(args, 1, design);
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for (auto module : design->selected_modules())
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for (auto &mem : Mem::get_selected_memories(module))
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{
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for (auto &port : mem.rd_ports)
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{
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if (port.clk_enable)
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log_error("Memory %s.%s has a synchronous read port. Synchronous read ports are not supported by memory_memx!\n",
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log_id(module), log_id(mem.memid));
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SigSpec addr_ok = make_addr_check(mem, port.addr);
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Wire *raw_rdata = module->addWire(NEW_ID, GetSize(port.data));
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module->addMux(NEW_ID, SigSpec(State::Sx, GetSize(port.data)), raw_rdata, addr_ok, port.data);
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port.data = raw_rdata;
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}
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for (auto &port : mem.wr_ports) {
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SigSpec addr_ok = make_addr_check(mem, port.addr);
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port.en = module->And(NEW_ID, port.en, addr_ok.repeat(GetSize(port.en)));
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}
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mem.emit();
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}
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}
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} MemoryMemxPass;
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PRIVATE_NAMESPACE_END
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