mirror of https://github.com/YosysHQ/yosys.git
56 lines
1.8 KiB
C++
56 lines
1.8 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/mem.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct MemoryCollectPass : public Pass {
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MemoryCollectPass() : Pass("memory_collect", "creating multi-port memory cells") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" memory_collect [selection]\n");
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log("\n");
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log("This pass collects memories and memory ports and creates generic multiport\n");
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log("memory cells.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override {
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log_header(design, "Executing MEMORY_COLLECT pass (generating $mem cells).\n");
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extra_args(args, 1, design);
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for (auto module : design->selected_modules()) {
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if (module->has_processes_warn())
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continue;
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for (auto &mem : Mem::get_selected_memories(module)) {
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if (!mem.packed) {
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mem.packed = true;
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mem.emit();
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}
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}
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}
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}
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} MemoryCollectPass;
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PRIVATE_NAMESPACE_END
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