mirror of https://github.com/YosysHQ/yosys.git
189 lines
6.2 KiB
C++
189 lines
6.2 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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* Copyright (C) 2012 Martin Schmölzer <martin@schmoelzer.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/log.h"
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#include "kernel/register.h"
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#include "kernel/sigtools.h"
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#include "kernel/consteval.h"
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#include "kernel/celltypes.h"
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#include "fsmdata.h"
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#include <string>
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#include <iostream>
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#include <fstream>
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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/**
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* Convert a signal into a KISS-compatible textual representation.
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*/
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std::string kiss_convert_signal(const RTLIL::SigSpec &sig) {
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log_assert(sig.is_fully_const());
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return sig.as_const().as_string();
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}
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/**
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* Create a KISS2 file from a cell.
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*
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* The destination file name is taken from the fsm_export attribute if present,
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* e.g. (* fsm_export="filename.kiss2" *). If this attribute is not present,
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* the file name will be assembled from the module and cell names.
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*
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* @param module pointer to module which contains the FSM cell.
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* @param cell pointer to the FSM cell which should be exported.
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*/
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void write_kiss2(struct RTLIL::Module *module, struct RTLIL::Cell *cell, std::string filename, bool origenc) {
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dict<RTLIL::IdString, RTLIL::Const>::iterator attr_it;
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FsmData fsm_data;
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FsmData::transition_t tr;
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std::ofstream kiss_file;
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std::string kiss_name;
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size_t i;
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attr_it = cell->attributes.find(ID::fsm_export);
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if (!filename.empty()) {
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kiss_name.assign(filename);
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} else if (attr_it != cell->attributes.end() && attr_it->second.decode_string() != "") {
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kiss_name.assign(attr_it->second.decode_string());
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}
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else {
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kiss_name.assign(log_id(module) + std::string("-") + log_id(cell) + ".kiss2");
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}
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log("\n");
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log("Exporting FSM `%s' from module `%s' to file `%s'.\n",
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cell->name.c_str(),
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module->name.c_str(),
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kiss_name.c_str());
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kiss_file.open(kiss_name, std::ios::out | std::ios::trunc);
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if (!kiss_file.is_open()) {
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log_error("Could not open file \"%s\" with write access.\n", kiss_name.c_str());
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}
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fsm_data.copy_from_cell(cell);
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kiss_file << ".i " << std::dec << fsm_data.num_inputs << std::endl;
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kiss_file << ".o " << std::dec << fsm_data.num_outputs << std::endl;
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kiss_file << ".p " << std::dec << fsm_data.transition_table.size() << std::endl;
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kiss_file << ".s " << std::dec << fsm_data.state_table.size() << std::endl;
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if (origenc) {
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kiss_file << ".r " << kiss_convert_signal(fsm_data.state_table[fsm_data.reset_state]) << std::endl;
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} else {
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kiss_file << ".r s" << std::dec << fsm_data.reset_state << std::endl;
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}
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for (i = 0; i < fsm_data.transition_table.size(); i++) {
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tr = fsm_data.transition_table[i];
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try {
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kiss_file << kiss_convert_signal(tr.ctrl_in) << ' ';
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if (origenc) {
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kiss_file << kiss_convert_signal(fsm_data.state_table[tr.state_in]) << ' ';
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kiss_file << kiss_convert_signal(fsm_data.state_table[tr.state_out]) << ' ';
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} else {
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kiss_file << 's' << tr.state_in << ' ';
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kiss_file << 's' << tr.state_out << ' ';
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}
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kiss_file << kiss_convert_signal(tr.ctrl_out) << std::endl;
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}
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catch (int) {
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kiss_file.close();
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log_error("exporting an FSM input or output signal failed.\n");
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}
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}
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kiss_file.close();
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}
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/**
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* Exports Finite State Machines in the design to one file per FSM. Currently,
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* only the KISS2 file format is supported.
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*/
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struct FsmExportPass : public Pass {
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FsmExportPass() : Pass("fsm_export", "exporting FSMs to KISS2 files") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" fsm_export [-noauto] [-o filename] [-origenc] [selection]\n");
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log("\n");
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log("This pass creates a KISS2 file for every selected FSM. For FSMs with the\n");
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log("'fsm_export' attribute set, the attribute value is used as filename, otherwise\n");
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log("the module and cell name is used as filename. If the parameter '-o' is given,\n");
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log("the first exported FSM is written to the specified filename. This overwrites\n");
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log("the setting as specified with the 'fsm_export' attribute. All other FSMs are\n");
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log("exported to the default name as mentioned above.\n");
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log("\n");
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log(" -noauto\n");
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log(" only export FSMs that have the 'fsm_export' attribute set\n");
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log("\n");
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log(" -o filename\n");
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log(" filename of the first exported FSM\n");
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log("\n");
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log(" -origenc\n");
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log(" use binary state encoding as state names instead of s0, s1, ...\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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dict<RTLIL::IdString, RTLIL::Const>::iterator attr_it;
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std::string arg;
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bool flag_noauto = false;
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std::string filename;
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bool flag_origenc = false;
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size_t argidx;
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log_header(design, "Executing FSM_EXPORT pass (exporting FSMs in KISS2 file format).\n");
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for (argidx = 1; argidx < args.size(); argidx++) {
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arg = args[argidx];
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if (arg == "-noauto") {
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flag_noauto = true;
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continue;
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}
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if (arg == "-o") {
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argidx++;
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filename = args[argidx];
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continue;
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}
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if (arg == "-origenc") {
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flag_origenc = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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for (auto mod : design->selected_modules())
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for (auto cell : mod->selected_cells())
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if (cell->type == ID($fsm)) {
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attr_it = cell->attributes.find(ID::fsm_export);
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if (!flag_noauto || (attr_it != cell->attributes.end())) {
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write_kiss2(mod, cell, filename, flag_origenc);
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filename.clear();
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}
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}
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}
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} FsmExportPass;
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PRIVATE_NAMESPACE_END
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