mirror of https://github.com/YosysHQ/yosys.git
350 lines
11 KiB
C++
350 lines
11 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/log.h"
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#include "kernel/register.h"
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#include "kernel/sigtools.h"
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#include "kernel/consteval.h"
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#include "kernel/celltypes.h"
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#include "fsmdata.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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static RTLIL::Module *module;
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static SigMap assign_map;
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typedef std::pair<RTLIL::Cell*, RTLIL::IdString> sig2driver_entry_t;
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static SigSet<sig2driver_entry_t> sig2driver, sig2user;
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static std::set<RTLIL::Cell*> muxtree_cells;
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static SigPool sig_at_port;
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static bool check_state_mux_tree(RTLIL::SigSpec old_sig, RTLIL::SigSpec sig, pool<Cell*> &recursion_monitor, dict<RTLIL::SigSpec, bool> &mux_tree_cache)
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{
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if (mux_tree_cache.find(sig) != mux_tree_cache.end())
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return mux_tree_cache.at(sig);
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if (sig.is_fully_const() || old_sig == sig) {
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ret_true:
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mux_tree_cache[sig] = true;
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return true;
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}
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if (sig_at_port.check_any(assign_map(sig))) {
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ret_false:
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mux_tree_cache[sig] = false;
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return false;
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}
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std::set<sig2driver_entry_t> cellport_list;
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sig2driver.find(sig, cellport_list);
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for (auto &cellport : cellport_list)
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{
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if ((cellport.first->type != ID($mux) && cellport.first->type != ID($pmux)) || cellport.second != ID::Y) {
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goto ret_false;
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}
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if (recursion_monitor.count(cellport.first)) {
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log_warning("logic loop in mux tree at signal %s in module %s.\n",
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log_signal(sig), RTLIL::id2cstr(module->name));
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goto ret_false;
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}
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recursion_monitor.insert(cellport.first);
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RTLIL::SigSpec sig_a = assign_map(cellport.first->getPort(ID::A));
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RTLIL::SigSpec sig_b = assign_map(cellport.first->getPort(ID::B));
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if (!check_state_mux_tree(old_sig, sig_a, recursion_monitor, mux_tree_cache)) {
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recursion_monitor.erase(cellport.first);
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goto ret_false;
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}
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for (int i = 0; i < sig_b.size(); i += sig_a.size())
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if (!check_state_mux_tree(old_sig, sig_b.extract(i, sig_a.size()), recursion_monitor, mux_tree_cache)) {
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recursion_monitor.erase(cellport.first);
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goto ret_false;
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}
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recursion_monitor.erase(cellport.first);
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muxtree_cells.insert(cellport.first);
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}
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goto ret_true;
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}
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static bool check_state_users(RTLIL::SigSpec sig)
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{
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if (sig_at_port.check_any(assign_map(sig)))
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return false;
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std::set<sig2driver_entry_t> cellport_list;
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sig2user.find(sig, cellport_list);
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for (auto &cellport : cellport_list) {
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RTLIL::Cell *cell = cellport.first;
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if (muxtree_cells.count(cell) > 0)
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continue;
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if (cell->type == ID($logic_not) && assign_map(cell->getPort(ID::A)) == sig)
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continue;
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if (cellport.second != ID::A && cellport.second != ID::B)
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return false;
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if (!cell->hasPort(ID::A) || !cell->hasPort(ID::B) || !cell->hasPort(ID::Y))
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return false;
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for (auto &port_it : cell->connections())
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if (port_it.first != ID::A && port_it.first != ID::B && port_it.first != ID::Y)
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return false;
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if (assign_map(cell->getPort(ID::A)) == sig && cell->getPort(ID::B).is_fully_const())
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continue;
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if (assign_map(cell->getPort(ID::B)) == sig && cell->getPort(ID::A).is_fully_const())
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continue;
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return false;
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}
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return true;
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}
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static void detect_fsm(RTLIL::Wire *wire, bool ignore_self_reset=false)
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{
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bool has_fsm_encoding_attr = wire->attributes.count(ID::fsm_encoding) > 0 && wire->attributes.at(ID::fsm_encoding).decode_string() != "none";
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bool has_fsm_encoding_none = wire->attributes.count(ID::fsm_encoding) > 0 && wire->attributes.at(ID::fsm_encoding).decode_string() == "none";
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bool has_init_attr = wire->attributes.count(ID::init) > 0;
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bool is_module_port = sig_at_port.check_any(assign_map(RTLIL::SigSpec(wire)));
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bool looks_like_state_reg = false, looks_like_good_state_reg = false;
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bool is_self_resetting = false;
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if (has_fsm_encoding_none)
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return;
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if (wire->width <= 1) {
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if (has_fsm_encoding_attr) {
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log_warning("Removing fsm_encoding attribute from 1-bit net: %s.%s\n", log_id(wire->module), log_id(wire));
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wire->attributes.erase(ID::fsm_encoding);
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}
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return;
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}
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std::set<sig2driver_entry_t> cellport_list;
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sig2driver.find(RTLIL::SigSpec(wire), cellport_list);
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for (auto &cellport : cellport_list)
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{
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if ((cellport.first->type != ID($dff) && cellport.first->type != ID($adff)) || cellport.second != ID::Q)
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continue;
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muxtree_cells.clear();
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pool<Cell*> recursion_monitor;
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RTLIL::SigSpec sig_q = assign_map(cellport.first->getPort(ID::Q));
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RTLIL::SigSpec sig_d = assign_map(cellport.first->getPort(ID::D));
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dict<RTLIL::SigSpec, bool> mux_tree_cache;
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if (sig_q != assign_map(wire))
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continue;
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looks_like_state_reg = check_state_mux_tree(sig_q, sig_d, recursion_monitor, mux_tree_cache);
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looks_like_good_state_reg = check_state_users(sig_q);
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if (!looks_like_state_reg)
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break;
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ConstEval ce(wire->module);
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std::set<sig2driver_entry_t> cellport_list;
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sig2user.find(sig_q, cellport_list);
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auto sig_q_bits = sig_q.to_sigbit_pool();
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for (auto &cellport : cellport_list)
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{
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RTLIL::Cell *cell = cellport.first;
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bool set_output = false, clr_output = false;
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if (cell->type.in(ID($ne), ID($reduce_or), ID($reduce_bool)))
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set_output = true;
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if (cell->type.in(ID($eq), ID($logic_not), ID($reduce_and)))
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clr_output = true;
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if (set_output || clr_output) {
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for (auto &port_it : cell->connections())
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if (cell->input(port_it.first))
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for (auto bit : assign_map(port_it.second))
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if (bit.wire != nullptr && !sig_q_bits.count(bit))
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goto next_cellport;
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}
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if (set_output || clr_output) {
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for (auto &port_it : cell->connections())
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if (cell->output(port_it.first)) {
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SigSpec sig = assign_map(port_it.second);
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Const val(set_output ? State::S1 : State::S0, GetSize(sig));
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ce.set(sig, val);
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}
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}
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next_cellport:;
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}
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SigSpec sig_y = sig_d, sig_undef;
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if (!ignore_self_reset && ce.eval(sig_y, sig_undef))
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is_self_resetting = true;
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}
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if (has_fsm_encoding_attr)
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{
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vector<string> warnings;
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if (is_module_port)
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warnings.push_back("Forcing FSM recoding on module port might result in larger circuit.\n");
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if (!looks_like_good_state_reg)
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warnings.push_back("Users of state reg look like FSM recoding might result in larger circuit.\n");
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if (has_init_attr)
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warnings.push_back("Initialization value on FSM state register is ignored. Possible simulation-synthesis mismatch!\n");
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if (!looks_like_state_reg)
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warnings.push_back("Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!\n");
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if (is_self_resetting)
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warnings.push_back("FSM seems to be self-resetting. Possible simulation-synthesis mismatch!\n");
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if (!warnings.empty()) {
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string warnmsg = stringf("Regarding the user-specified fsm_encoding attribute on %s.%s:\n", log_id(wire->module), log_id(wire));
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for (auto w : warnings) warnmsg += " " + w;
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log_warning("%s", warnmsg.c_str());
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} else {
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log("FSM state register %s.%s already has fsm_encoding attribute.\n", log_id(wire->module), log_id(wire));
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}
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}
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else
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if (looks_like_state_reg && looks_like_good_state_reg && !has_init_attr && !is_module_port && !is_self_resetting)
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{
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log("Found FSM state register %s.%s.\n", log_id(wire->module), log_id(wire));
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wire->attributes[ID::fsm_encoding] = RTLIL::Const("auto");
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}
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else
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if (looks_like_state_reg)
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{
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log("Not marking %s.%s as FSM state register:\n", log_id(wire->module), log_id(wire));
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if (is_module_port)
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log(" Register is connected to module port.\n");
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if (!looks_like_good_state_reg)
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log(" Users of register don't seem to benefit from recoding.\n");
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if (has_init_attr)
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log(" Register has an initialization value.\n");
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if (is_self_resetting)
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log(" Circuit seems to be self-resetting.\n");
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}
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}
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struct FsmDetectPass : public Pass {
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FsmDetectPass() : Pass("fsm_detect", "finding FSMs in design") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" fsm_detect [options] [selection]\n");
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log("\n");
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log("This pass detects finite state machines by identifying the state signal.\n");
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log("The state signal is then marked by setting the attribute 'fsm_encoding'\n");
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log("on the state signal to \"auto\".\n");
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log("\n");
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log(" -ignore-self-reset\n");
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log(" Mark FSMs even if they are self-resetting\n");
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log("\n");
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log("Existing 'fsm_encoding' attributes are not changed by this pass.\n");
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log("\n");
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log("Signals can be protected from being detected by this pass by setting the\n");
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log("'fsm_encoding' attribute to \"none\".\n");
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log("\n");
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log("This pass uses a subset of FF types to detect FSMs. Run 'opt -nosdff -nodffe'\n");
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log("before this pass to prepare the design for fsm_detect.\n");
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log("\n");
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#ifdef YOSYS_ENABLE_VERIFIC
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log("The Verific frontend may optimize the design in a way that interferes with FSM\n");
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log("detection. Run 'verific -cfg db_infer_wide_muxes_post_elaboration 0' before\n");
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log("reading the source, and 'bmuxmap -pmux' after 'proc' for best results.\n");
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log("\n");
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#endif
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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log_header(design, "Executing FSM_DETECT pass (finding FSMs in design).\n");
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bool ignore_self_reset = false;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-ignore-self-reset") {
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ignore_self_reset = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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CellTypes ct;
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ct.setup_internals();
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ct.setup_internals_anyinit();
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ct.setup_internals_mem();
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ct.setup_stdcells();
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ct.setup_stdcells_mem();
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for (auto mod : design->selected_modules())
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{
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module = mod;
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assign_map.set(module);
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sig2driver.clear();
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sig2user.clear();
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sig_at_port.clear();
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for (auto cell : module->cells())
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for (auto &conn_it : cell->connections()) {
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if (ct.cell_output(cell->type, conn_it.first) || !ct.cell_known(cell->type)) {
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RTLIL::SigSpec sig = conn_it.second;
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assign_map.apply(sig);
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sig2driver.insert(sig, sig2driver_entry_t(cell, conn_it.first));
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}
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if (!ct.cell_known(cell->type) || ct.cell_input(cell->type, conn_it.first)) {
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RTLIL::SigSpec sig = conn_it.second;
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assign_map.apply(sig);
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sig2user.insert(sig, sig2driver_entry_t(cell, conn_it.first));
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}
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}
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for (auto wire : module->wires())
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if (wire->port_id != 0)
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sig_at_port.add(assign_map(wire));
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for (auto wire : module->selected_wires())
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detect_fsm(wire, ignore_self_reset);
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}
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assign_map.clear();
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sig2driver.clear();
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sig2user.clear();
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muxtree_cells.clear();
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}
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} FsmDetectPass;
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PRIVATE_NAMESPACE_END
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