mirror of https://github.com/YosysHQ/yosys.git
124 lines
3.8 KiB
C++
124 lines
3.8 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/celltypes.h"
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#include "kernel/sigtools.h"
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#include "kernel/utils.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct TorderPass : public Pass {
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TorderPass() : Pass("torder", "print cells in topological order") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" torder [options] [selection]\n");
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log("\n");
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log("This command prints the selected cells in topological order.\n");
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log("\n");
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log(" -stop <cell_type> <cell_port>\n");
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log(" do not use the specified cell port in topological sorting\n");
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log("\n");
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log(" -noautostop\n");
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log(" by default Q outputs of internal FF cells and memory read port outputs\n");
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log(" are not used in topological sorting. this option deactivates that.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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bool noautostop = false;
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dict<IdString, pool<IdString>> stop_db;
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log_header(design, "Executing TORDER pass (print cells in topological order).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-stop" && argidx+2 < args.size()) {
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IdString cell_type = RTLIL::escape_id(args[++argidx]);
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IdString cell_port = RTLIL::escape_id(args[++argidx]);
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stop_db[cell_type].insert(cell_port);
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continue;
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}
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if (args[argidx] == "-noautostop") {
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noautostop = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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for (auto module : design->selected_modules())
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{
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log("module %s\n", log_id(module));
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SigMap sigmap(module);
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dict<SigBit, pool<IdString>> bit_drivers, bit_users;
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TopoSort<IdString, RTLIL::sort_by_id_str> toposort;
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for (auto cell : module->selected_cells())
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for (auto conn : cell->connections())
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{
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if (stop_db.count(cell->type) && stop_db.at(cell->type).count(conn.first))
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continue;
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if (!noautostop && yosys_celltypes.cell_known(cell->type)) {
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if (conn.first.in(ID::Q, ID::CTRL_OUT, ID::RD_DATA))
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continue;
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if (cell->type.in(ID($memrd), ID($memrd_v2)) && conn.first == ID::DATA)
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continue;
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}
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if (cell->input(conn.first))
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for (auto bit : sigmap(conn.second))
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bit_users[bit].insert(cell->name);
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if (cell->output(conn.first))
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for (auto bit : sigmap(conn.second))
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bit_drivers[bit].insert(cell->name);
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toposort.node(cell->name);
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}
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for (auto &it : bit_users)
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if (bit_drivers.count(it.first))
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for (auto driver_cell : bit_drivers.at(it.first))
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for (auto user_cell : it.second)
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toposort.edge(driver_cell, user_cell);
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toposort.analyze_loops = true;
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toposort.sort();
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for (auto &it : toposort.loops) {
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log(" loop");
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for (auto cell : it)
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log(" %s", log_id(cell));
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log("\n");
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}
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for (auto cell : toposort.sorted)
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log(" cell %s\n", log_id(cell));
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}
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}
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} TorderPass;
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PRIVATE_NAMESPACE_END
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