mirror of https://github.com/YosysHQ/yosys.git
23 lines
649 B
Python
Executable File
23 lines
649 B
Python
Executable File
#!/usr/bin/python3
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from pyosys import libyosys as ys
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import matplotlib.pyplot as plt
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import numpy as np
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design = ys.Design()
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ys.run_pass("read_verilog ../../tests/simple/fiedler-cooley.v", design);
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ys.run_pass("prep", design)
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ys.run_pass("opt -full", design)
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cell_stats = {}
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for module in design.selected_whole_modules_warn():
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for cell in module.selected_cells():
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if cell.type.str() in cell_stats:
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cell_stats[cell.type.str()] += 1
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else:
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cell_stats[cell.type.str()] = 1
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plt.bar(range(len(cell_stats)), height = list(cell_stats.values()),align='center')
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plt.xticks(range(len(cell_stats)), list(cell_stats.keys()))
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plt.show()
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