mirror of https://github.com/YosysHQ/yosys.git
19 lines
380 B
Verilog
19 lines
380 B
Verilog
module demo (
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input wire CLK_IN,
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output wire R_LED
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);
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parameter time1 = 30'd12_000_000;
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reg led_state;
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reg [29:0] count;
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always @(posedge CLK_IN)begin
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if(count == time1)begin
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count<= 30'd0;
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led_state <= ~led_state;
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end
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else
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count <= count + 1'b1;
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end
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assign R_LED = led_state;
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endmodule
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