mirror of https://github.com/YosysHQ/yosys.git
701 lines
23 KiB
C++
701 lines
23 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/rtlil.h"
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#include "kernel/register.h"
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#include "kernel/sigtools.h"
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#include "kernel/celltypes.h"
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#include "kernel/cellaigs.h"
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#include "kernel/log.h"
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#include <string>
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct JsonWriter
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{
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std::ostream &f;
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bool aig_mode;
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bool compat_int_mode;
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Design *design;
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Module *module;
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SigMap sigmap;
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int sigidcounter;
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dict<SigBit, string> sigids;
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pool<Aig> aig_models;
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JsonWriter(std::ostream &f, bool aig_mode, bool compat_int_mode) :
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f(f), aig_mode(aig_mode), compat_int_mode(compat_int_mode) { }
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string get_string(string str)
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{
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string newstr = "\"";
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for (char c : str) {
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if (c == '\\')
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newstr += "\\\\";
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else if (c == '"')
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newstr += "\\\"";
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else if (c == '\b')
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newstr += "\\b";
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else if (c == '\f')
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newstr += "\\f";
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else if (c == '\n')
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newstr += "\\n";
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else if (c == '\r')
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newstr += "\\r";
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else if (c == '\t')
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newstr += "\\t";
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else if (c < 0x20)
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newstr += stringf("\\u%04X", c);
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else
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newstr += c;
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}
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return newstr + "\"";
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}
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string get_name(IdString name)
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{
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return get_string(RTLIL::unescape_id(name));
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}
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string get_bits(SigSpec sig)
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{
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bool first = true;
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string str = "[";
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for (auto bit : sigmap(sig)) {
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str += first ? " " : ", ";
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first = false;
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if (sigids.count(bit) == 0) {
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string &s = sigids[bit];
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if (bit.wire == nullptr) {
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if (bit == State::S0) s = "\"0\"";
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else if (bit == State::S1) s = "\"1\"";
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else if (bit == State::Sz) s = "\"z\"";
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else s = "\"x\"";
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} else
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s = stringf("%d", sigidcounter++);
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}
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str += sigids[bit];
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}
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return str + " ]";
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}
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void write_parameter_value(const Const &value)
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{
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if ((value.flags & RTLIL::ConstFlags::CONST_FLAG_STRING) != 0) {
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string str = value.decode_string();
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int state = 0;
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for (char c : str) {
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if (state == 0) {
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if (c == '0' || c == '1' || c == 'x' || c == 'z')
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state = 0;
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else if (c == ' ')
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state = 1;
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else
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state = 2;
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} else if (state == 1 && c != ' ')
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state = 2;
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}
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if (state < 2)
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str += " ";
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f << get_string(str);
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} else if (compat_int_mode && GetSize(value) <= 32 && value.is_fully_def()) {
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if ((value.flags & RTLIL::ConstFlags::CONST_FLAG_SIGNED) != 0)
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f << stringf("%d", value.as_int());
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else
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f << stringf("%u", value.as_int());
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} else {
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f << get_string(value.as_string());
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}
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}
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void write_parameters(const dict<IdString, Const> ¶meters, bool for_module=false)
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{
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bool first = true;
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for (auto ¶m : parameters) {
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f << stringf("%s\n", first ? "" : ",");
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f << stringf(" %s%s: ", for_module ? "" : " ", get_name(param.first).c_str());
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write_parameter_value(param.second);
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first = false;
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}
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}
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void write_module(Module *module_)
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{
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module = module_;
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log_assert(module->design == design);
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sigmap.set(module);
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sigids.clear();
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// reserve 0 and 1 to avoid confusion with "0" and "1"
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sigidcounter = 2;
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if (module->has_processes()) {
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log_error("Module %s contains processes, which are not supported by JSON backend (run `proc` first).\n", log_id(module));
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}
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f << stringf(" %s: {\n", get_name(module->name).c_str());
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f << stringf(" \"attributes\": {");
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write_parameters(module->attributes, /*for_module=*/true);
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f << stringf("\n },\n");
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if (module->parameter_default_values.size()) {
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f << stringf(" \"parameter_default_values\": {");
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write_parameters(module->parameter_default_values, /*for_module=*/true);
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f << stringf("\n },\n");
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}
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f << stringf(" \"ports\": {");
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bool first = true;
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for (auto n : module->ports) {
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Wire *w = module->wire(n);
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if (!module->selected(w))
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continue;
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f << stringf("%s\n", first ? "" : ",");
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f << stringf(" %s: {\n", get_name(n).c_str());
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f << stringf(" \"direction\": \"%s\",\n", w->port_input ? w->port_output ? "inout" : "input" : "output");
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if (w->start_offset)
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f << stringf(" \"offset\": %d,\n", w->start_offset);
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if (w->upto)
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f << stringf(" \"upto\": 1,\n");
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if (w->is_signed)
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f << stringf(" \"signed\": %d,\n", w->is_signed);
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f << stringf(" \"bits\": %s\n", get_bits(w).c_str());
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f << stringf(" }");
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first = false;
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}
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f << stringf("\n },\n");
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f << stringf(" \"cells\": {");
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first = true;
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for (auto c : module->selected_cells()) {
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// Eventually we will want to emit $scopeinfo, but currently this
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// will break JSON netlist consumers like nextpnr
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if (c->type == ID($scopeinfo))
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continue;
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f << stringf("%s\n", first ? "" : ",");
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f << stringf(" %s: {\n", get_name(c->name).c_str());
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f << stringf(" \"hide_name\": %s,\n", c->name[0] == '$' ? "1" : "0");
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f << stringf(" \"type\": %s,\n", get_name(c->type).c_str());
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if (aig_mode) {
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Aig aig(c);
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if (!aig.name.empty()) {
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f << stringf(" \"model\": \"%s\",\n", aig.name.c_str());
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aig_models.insert(aig);
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}
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}
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f << stringf(" \"parameters\": {");
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write_parameters(c->parameters);
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f << stringf("\n },\n");
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f << stringf(" \"attributes\": {");
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write_parameters(c->attributes);
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f << stringf("\n },\n");
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if (c->known()) {
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f << stringf(" \"port_directions\": {");
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bool first2 = true;
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for (auto &conn : c->connections()) {
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string direction = "output";
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if (c->input(conn.first))
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direction = c->output(conn.first) ? "inout" : "input";
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f << stringf("%s\n", first2 ? "" : ",");
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f << stringf(" %s: \"%s\"", get_name(conn.first).c_str(), direction.c_str());
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first2 = false;
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}
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f << stringf("\n },\n");
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}
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f << stringf(" \"connections\": {");
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bool first2 = true;
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for (auto &conn : c->connections()) {
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f << stringf("%s\n", first2 ? "" : ",");
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f << stringf(" %s: %s", get_name(conn.first).c_str(), get_bits(conn.second).c_str());
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first2 = false;
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}
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f << stringf("\n }\n");
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f << stringf(" }");
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first = false;
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}
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f << stringf("\n },\n");
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if (module->has_memories()) {
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f << stringf(" \"memories\": {");
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first = true;
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for (auto m : module->selected_memories()) {
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f << stringf("%s\n", first ? "" : ",");
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f << stringf(" %s: {\n", get_name(m->name).c_str());
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f << stringf(" \"hide_name\": %s,\n", m->name[0] == '$' ? "1" : "0");
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f << stringf(" \"attributes\": {");
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write_parameters(m->attributes);
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f << stringf("\n },\n");
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f << stringf(" \"width\": %d,\n", m->width);
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f << stringf(" \"start_offset\": %d,\n", m->start_offset);
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f << stringf(" \"size\": %d\n", m->size);
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f << stringf(" }");
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first = false;
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}
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f << stringf("\n },\n");
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}
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f << stringf(" \"netnames\": {");
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first = true;
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for (auto w : module->selected_wires()) {
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f << stringf("%s\n", first ? "" : ",");
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f << stringf(" %s: {\n", get_name(w->name).c_str());
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f << stringf(" \"hide_name\": %s,\n", w->name[0] == '$' ? "1" : "0");
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f << stringf(" \"bits\": %s,\n", get_bits(w).c_str());
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if (w->start_offset)
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f << stringf(" \"offset\": %d,\n", w->start_offset);
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if (w->upto)
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f << stringf(" \"upto\": 1,\n");
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if (w->is_signed)
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f << stringf(" \"signed\": %d,\n", w->is_signed);
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f << stringf(" \"attributes\": {");
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write_parameters(w->attributes);
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f << stringf("\n }\n");
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f << stringf(" }");
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first = false;
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}
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f << stringf("\n }\n");
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f << stringf(" }");
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}
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void write_design(Design *design_)
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{
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design = design_;
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design->sort();
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f << stringf("{\n");
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f << stringf(" \"creator\": %s,\n", get_string(yosys_version_str).c_str());
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f << stringf(" \"modules\": {\n");
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bool first_module = true;
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for (auto mod : design->all_selected_modules()) {
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if (!first_module)
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f << stringf(",\n");
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write_module(mod);
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first_module = false;
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}
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f << stringf("\n }");
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if (!aig_models.empty()) {
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f << stringf(",\n \"models\": {\n");
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bool first_model = true;
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for (auto &aig : aig_models) {
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if (!first_model)
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f << stringf(",\n");
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f << stringf(" \"%s\": [\n", aig.name.c_str());
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int node_idx = 0;
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for (auto &node : aig.nodes) {
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if (node_idx != 0)
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f << stringf(",\n");
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f << stringf(" /* %3d */ [ ", node_idx);
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if (node.portbit >= 0)
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f << stringf("\"%sport\", \"%s\", %d", node.inverter ? "n" : "",
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log_id(node.portname), node.portbit);
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else if (node.left_parent < 0 && node.right_parent < 0)
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f << stringf("\"%s\"", node.inverter ? "true" : "false");
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else
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f << stringf("\"%s\", %d, %d", node.inverter ? "nand" : "and", node.left_parent, node.right_parent);
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for (auto &op : node.outports)
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f << stringf(", \"%s\", %d", log_id(op.first), op.second);
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f << stringf(" ]");
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node_idx++;
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}
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f << stringf("\n ]");
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first_model = false;
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}
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f << stringf("\n }");
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}
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f << stringf("\n}\n");
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}
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};
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struct JsonBackend : public Backend {
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JsonBackend() : Backend("json", "write design to a JSON file") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" write_json [options] [filename]\n");
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log("\n");
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log("Write a JSON netlist of the current design.\n");
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log("\n");
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log(" -aig\n");
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log(" include AIG models for the different gate types\n");
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log("\n");
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log(" -compat-int\n");
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log(" emit 32-bit or smaller fully-defined parameter values directly\n");
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log(" as JSON numbers (for compatibility with old parsers)\n");
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log("\n");
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log(" -selected\n");
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log(" only write selected parts of the design.\n");
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log("\n");
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log("\n");
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log("The general syntax of the JSON output created by this command is as follows:\n");
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log("\n");
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log(" {\n");
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log(" \"creator\": \"Yosys <version info>\",\n");
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log(" \"modules\": {\n");
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log(" <module_name>: {\n");
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log(" \"attributes\": {\n");
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log(" <attribute_name>: <attribute_value>,\n");
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log(" ...\n");
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log(" },\n");
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log(" \"parameter_default_values\": {\n");
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log(" <parameter_name>: <parameter_value>,\n");
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log(" ...\n");
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log(" },\n");
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log(" \"ports\": {\n");
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log(" <port_name>: <port_details>,\n");
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log(" ...\n");
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log(" },\n");
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log(" \"cells\": {\n");
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log(" <cell_name>: <cell_details>,\n");
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log(" ...\n");
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log(" },\n");
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log(" \"memories\": {\n");
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log(" <memory_name>: <memory_details>,\n");
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log(" ...\n");
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log(" },\n");
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log(" \"netnames\": {\n");
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log(" <net_name>: <net_details>,\n");
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log(" ...\n");
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log(" }\n");
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log(" }\n");
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log(" },\n");
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log(" \"models\": {\n");
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log(" ...\n");
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log(" },\n");
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log(" }\n");
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log("\n");
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log("Where <port_details> is:\n");
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log("\n");
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log(" {\n");
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log(" \"direction\": <\"input\" | \"output\" | \"inout\">,\n");
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log(" \"bits\": <bit_vector>\n");
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log(" \"offset\": <the lowest bit index in use, if non-0>\n");
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log(" \"upto\": <1 if the port bit indexing is MSB-first>\n");
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log(" \"signed\": <1 if the port is signed>\n");
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log(" }\n");
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log("\n");
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log("The \"offset\" and \"upto\" fields are skipped if their value would be 0.\n");
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log("They don't affect connection semantics, and are only used to preserve original\n");
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log("HDL bit indexing.");
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log("And <cell_details> is:\n");
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log("\n");
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log(" {\n");
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log(" \"hide_name\": <1 | 0>,\n");
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log(" \"type\": <cell_type>,\n");
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log(" \"model\": <AIG model name, if -aig option used>,\n");
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log(" \"parameters\": {\n");
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log(" <parameter_name>: <parameter_value>,\n");
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log(" ...\n");
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log(" },\n");
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log(" \"attributes\": {\n");
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log(" <attribute_name>: <attribute_value>,\n");
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log(" ...\n");
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log(" },\n");
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log(" \"port_directions\": {\n");
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log(" <port_name>: <\"input\" | \"output\" | \"inout\">,\n");
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log(" ...\n");
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log(" },\n");
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log(" \"connections\": {\n");
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log(" <port_name>: <bit_vector>,\n");
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log(" ...\n");
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log(" },\n");
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log(" }\n");
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log("\n");
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log("And <memory_details> is:\n");
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log("\n");
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log(" {\n");
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log(" \"hide_name\": <1 | 0>,\n");
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log(" \"attributes\": {\n");
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log(" <attribute_name>: <attribute_value>,\n");
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log(" ...\n");
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log(" },\n");
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log(" \"width\": <memory width>\n");
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log(" \"start_offset\": <the lowest valid memory address>\n");
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log(" \"size\": <memory size>\n");
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log(" }\n");
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log("\n");
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log("And <net_details> is:\n");
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log("\n");
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log(" {\n");
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log(" \"hide_name\": <1 | 0>,\n");
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log(" \"bits\": <bit_vector>\n");
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log(" \"offset\": <the lowest bit index in use, if non-0>\n");
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log(" \"upto\": <1 if the port bit indexing is MSB-first>\n");
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log(" \"signed\": <1 if the port is signed>\n");
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log(" }\n");
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log("\n");
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log("The \"hide_name\" fields are set to 1 when the name of this cell or net is\n");
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log("automatically created and is likely not of interest for a regular user.\n");
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log("\n");
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log("The \"port_directions\" section is only included for cells for which the\n");
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log("interface is known.\n");
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log("\n");
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log("Module and cell ports and nets can be single bit wide or vectors of multiple\n");
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log("bits. Each individual signal bit is assigned a unique integer. The <bit_vector>\n");
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log("values referenced above are vectors of this integers. Signal bits that are\n");
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log("connected to a constant driver are denoted as string \"0\", \"1\", \"x\", or\n");
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log("\"z\" instead of a number.\n");
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log("\n");
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log("Bit vectors (including integers) are written as string holding the binary\n");
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log("representation of the value. Strings are written as strings, with an appended\n");
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log("blank in cases of strings of the form /[01xz]* */.\n");
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log("\n");
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log("For example the following Verilog code:\n");
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log("\n");
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log(" module test(input x, y);\n");
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log(" (* keep *) foo #(.P(42), .Q(1337))\n");
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log(" foo_inst (.A({x, y}), .B({y, x}), .C({4'd10, {4{x}}}));\n");
|
|
log(" endmodule\n");
|
|
log("\n");
|
|
log("Translates to the following JSON output:\n");
|
|
log("\n");
|
|
|
|
log(" {\n");
|
|
log(" \"creator\": \"Yosys 0.9+2406 (git sha1 fb1168d8, clang 9.0.1 -fPIC -Os)\",\n");
|
|
log(" \"modules\": {\n");
|
|
log(" \"test\": {\n");
|
|
log(" \"attributes\": {\n");
|
|
log(" \"cells_not_processed\": \"00000000000000000000000000000001\",\n");
|
|
log(" \"src\": \"test.v:1.1-4.10\"\n");
|
|
log(" },\n");
|
|
log(" \"ports\": {\n");
|
|
log(" \"x\": {\n");
|
|
log(" \"direction\": \"input\",\n");
|
|
log(" \"bits\": [ 2 ]\n");
|
|
log(" },\n");
|
|
log(" \"y\": {\n");
|
|
log(" \"direction\": \"input\",\n");
|
|
log(" \"bits\": [ 3 ]\n");
|
|
log(" }\n");
|
|
log(" },\n");
|
|
log(" \"cells\": {\n");
|
|
log(" \"foo_inst\": {\n");
|
|
log(" \"hide_name\": 0,\n");
|
|
log(" \"type\": \"foo\",\n");
|
|
log(" \"parameters\": {\n");
|
|
log(" \"P\": \"00000000000000000000000000101010\",\n");
|
|
log(" \"Q\": \"00000000000000000000010100111001\"\n");
|
|
log(" },\n");
|
|
log(" \"attributes\": {\n");
|
|
log(" \"keep\": \"00000000000000000000000000000001\",\n");
|
|
log(" \"module_not_derived\": \"00000000000000000000000000000001\",\n");
|
|
log(" \"src\": \"test.v:3.1-3.55\"\n");
|
|
log(" },\n");
|
|
log(" \"connections\": {\n");
|
|
log(" \"A\": [ 3, 2 ],\n");
|
|
log(" \"B\": [ 2, 3 ],\n");
|
|
log(" \"C\": [ 2, 2, 2, 2, \"0\", \"1\", \"0\", \"1\" ]\n");
|
|
log(" }\n");
|
|
log(" }\n");
|
|
log(" },\n");
|
|
log(" \"netnames\": {\n");
|
|
log(" \"x\": {\n");
|
|
log(" \"hide_name\": 0,\n");
|
|
log(" \"bits\": [ 2 ],\n");
|
|
log(" \"attributes\": {\n");
|
|
log(" \"src\": \"test.v:1.19-1.20\"\n");
|
|
log(" }\n");
|
|
log(" },\n");
|
|
log(" \"y\": {\n");
|
|
log(" \"hide_name\": 0,\n");
|
|
log(" \"bits\": [ 3 ],\n");
|
|
log(" \"attributes\": {\n");
|
|
log(" \"src\": \"test.v:1.22-1.23\"\n");
|
|
log(" }\n");
|
|
log(" }\n");
|
|
log(" }\n");
|
|
log(" }\n");
|
|
log(" }\n");
|
|
log(" }\n");
|
|
log("\n");
|
|
log("The models are given as And-Inverter-Graphs (AIGs) in the following form:\n");
|
|
log("\n");
|
|
log(" \"models\": {\n");
|
|
log(" <model_name>: [\n");
|
|
log(" /* 0 */ [ <node-spec> ],\n");
|
|
log(" /* 1 */ [ <node-spec> ],\n");
|
|
log(" /* 2 */ [ <node-spec> ],\n");
|
|
log(" ...\n");
|
|
log(" ],\n");
|
|
log(" ...\n");
|
|
log(" },\n");
|
|
log("\n");
|
|
log("The following node-types may be used:\n");
|
|
log("\n");
|
|
log(" [ \"port\", <portname>, <bitindex>, <out-list> ]\n");
|
|
log(" - the value of the specified input port bit\n");
|
|
log("\n");
|
|
log(" [ \"nport\", <portname>, <bitindex>, <out-list> ]\n");
|
|
log(" - the inverted value of the specified input port bit\n");
|
|
log("\n");
|
|
log(" [ \"and\", <node-index>, <node-index>, <out-list> ]\n");
|
|
log(" - the ANDed value of the specified nodes\n");
|
|
log("\n");
|
|
log(" [ \"nand\", <node-index>, <node-index>, <out-list> ]\n");
|
|
log(" - the inverted ANDed value of the specified nodes\n");
|
|
log("\n");
|
|
log(" [ \"true\", <out-list> ]\n");
|
|
log(" - the constant value 1\n");
|
|
log("\n");
|
|
log(" [ \"false\", <out-list> ]\n");
|
|
log(" - the constant value 0\n");
|
|
log("\n");
|
|
log("All nodes appear in topological order. I.e. only nodes with smaller indices\n");
|
|
log("are referenced by \"and\" and \"nand\" nodes.\n");
|
|
log("\n");
|
|
log("The optional <out-list> at the end of a node specification is a list of\n");
|
|
log("output portname and bitindex pairs, specifying the outputs driven by this node.\n");
|
|
log("\n");
|
|
log("For example, the following is the model for a 3-input 3-output $reduce_and cell\n");
|
|
log("inferred by the following code:\n");
|
|
log("\n");
|
|
log(" module test(input [2:0] in, output [2:0] out);\n");
|
|
log(" assign in = &out;\n");
|
|
log(" endmodule\n");
|
|
log("\n");
|
|
log(" \"$reduce_and:3U:3\": [\n");
|
|
log(" /* 0 */ [ \"port\", \"A\", 0 ],\n");
|
|
log(" /* 1 */ [ \"port\", \"A\", 1 ],\n");
|
|
log(" /* 2 */ [ \"and\", 0, 1 ],\n");
|
|
log(" /* 3 */ [ \"port\", \"A\", 2 ],\n");
|
|
log(" /* 4 */ [ \"and\", 2, 3, \"Y\", 0 ],\n");
|
|
log(" /* 5 */ [ \"false\", \"Y\", 1, \"Y\", 2 ]\n");
|
|
log(" ]\n");
|
|
log("\n");
|
|
log("Future version of Yosys might add support for additional fields in the JSON\n");
|
|
log("format. A program processing this format must ignore all unknown fields.\n");
|
|
log("\n");
|
|
}
|
|
void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
|
|
{
|
|
bool aig_mode = false;
|
|
bool compat_int_mode = false;
|
|
bool use_selection = false;
|
|
|
|
size_t argidx;
|
|
for (argidx = 1; argidx < args.size(); argidx++)
|
|
{
|
|
if (args[argidx] == "-aig") {
|
|
aig_mode = true;
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-compat-int") {
|
|
compat_int_mode = true;
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-selected") {
|
|
use_selection = true;
|
|
continue;
|
|
}
|
|
break;
|
|
}
|
|
extra_args(f, filename, args, argidx);
|
|
|
|
log_header(design, "Executing JSON backend.\n");
|
|
|
|
if (!use_selection) design->push_complete_selection();
|
|
JsonWriter json_writer(*f, aig_mode, compat_int_mode);
|
|
json_writer.write_design(design);
|
|
if (!use_selection) design->pop_selection();
|
|
}
|
|
} JsonBackend;
|
|
|
|
struct JsonPass : public Pass {
|
|
JsonPass() : Pass("json", "write design in JSON format") { }
|
|
void help() override
|
|
{
|
|
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
|
log("\n");
|
|
log(" json [options] [selection]\n");
|
|
log("\n");
|
|
log("Write a JSON netlist of all selected objects.\n");
|
|
log("\n");
|
|
log(" -o <filename>\n");
|
|
log(" write to the specified file.\n");
|
|
log("\n");
|
|
log(" -aig\n");
|
|
log(" also include AIG models for the different gate types\n");
|
|
log("\n");
|
|
log(" -compat-int\n");
|
|
log(" emit 32-bit or smaller fully-defined parameter values directly\n");
|
|
log(" as JSON numbers (for compatibility with old parsers)\n");
|
|
log("\n");
|
|
log("See 'help write_json' for a description of the JSON format used.\n");
|
|
log("\n");
|
|
}
|
|
void execute(std::vector<std::string> args, RTLIL::Design *design) override
|
|
{
|
|
std::string filename;
|
|
bool aig_mode = false;
|
|
bool compat_int_mode = false;
|
|
|
|
size_t argidx;
|
|
for (argidx = 1; argidx < args.size(); argidx++)
|
|
{
|
|
if (args[argidx] == "-o" && argidx+1 < args.size()) {
|
|
filename = args[++argidx];
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-aig") {
|
|
aig_mode = true;
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-compat-int") {
|
|
compat_int_mode = true;
|
|
continue;
|
|
}
|
|
break;
|
|
}
|
|
extra_args(args, argidx, design);
|
|
|
|
std::ostream *f;
|
|
std::stringstream buf;
|
|
bool empty = filename.empty();
|
|
|
|
if (!empty) {
|
|
rewrite_filename(filename);
|
|
std::ofstream *ff = new std::ofstream;
|
|
ff->open(filename.c_str(), std::ofstream::trunc);
|
|
if (ff->fail()) {
|
|
delete ff;
|
|
log_error("Can't open file `%s' for writing: %s\n", filename.c_str(), strerror(errno));
|
|
}
|
|
f = ff;
|
|
} else {
|
|
f = &buf;
|
|
}
|
|
|
|
JsonWriter json_writer(*f, aig_mode, compat_int_mode);
|
|
json_writer.write_design(design);
|
|
|
|
if (!empty) {
|
|
delete f;
|
|
} else {
|
|
log("%s", buf.str().c_str());
|
|
}
|
|
}
|
|
} JsonPass;
|
|
|
|
PRIVATE_NAMESPACE_END
|